Light emission and enhanced nonlinearity in nanophotonic waveguide circuits by III–V/silicon-on-insulator heterogeneous integration

2008 ◽  
Vol 104 (3) ◽  
pp. 033117 ◽  
Author(s):  
G. Roelkens ◽  
L. Liu ◽  
D. Van Thourhout ◽  
R. Baets ◽  
R. Nötzel ◽  
...  
2016 ◽  
Vol 13 (2) ◽  
pp. 71-76 ◽  
Author(s):  
Colin McDonough ◽  
Doug La Tulipe ◽  
Dan Pascual ◽  
Paul Tariello ◽  
John Mucci ◽  
...  

A fully functional Si photonics and 65-nm complementary metal-oxide semiconductor (CMOS) heterogeneous three-dimensional (3-D) integration is demonstrated for the first time in a 300-mm production environment. Direct oxide wafer bonding was developed to eliminate voids between silicon on insulator photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via 3-D integration was developed for low capacitance electrical connections with no impact on the CMOS performance. The 3-D yield approaching 100% was demonstrated on >20,000 via chains.


2011 ◽  
Vol 23 (23) ◽  
pp. 1760-1762 ◽  
Author(s):  
Nannicha Hattasan ◽  
Alban Gassenq ◽  
Laurent Cerutti ◽  
Jean-Baptiste Rodriguez ◽  
Eric Tournie ◽  
...  

AIP Advances ◽  
2018 ◽  
Vol 8 (5) ◽  
pp. 055323 ◽  
Author(s):  
Runchun Zhang ◽  
Beiji Zhao ◽  
Kai Huang ◽  
Tiangui You ◽  
Qi Jia ◽  
...  

Author(s):  
Mark W. Jenkins ◽  
Paiboon Tangyunyong ◽  
Edward I. Cole ◽  
Jerry M. Soden ◽  
Jeremy A. Walraven ◽  
...  

Abstract Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.


Sign in / Sign up

Export Citation Format

Share Document