Silicon-oxide-nitride-oxide-silicon-type flash memory with a high-k NdTiO3 charge trapping layer

2008 ◽  
Vol 92 (11) ◽  
pp. 112906 ◽  
Author(s):  
Tung-Ming Pan ◽  
Te-Yi Yu
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Charge Trapping ◽  
High K ◽  
Nitride Oxide

scholarly journals Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 356 ◽  
Author(s):  
Seung-Dong Yang ◽  
Jun-Kyo Jung ◽  
Jae-Gab Lim ◽  
Seong-gye Park ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Photoelectron Spectroscopy ◽  
Flash Memory ◽  
Silicon Oxide ◽  
Charge Trapping ◽  
Charge Migration ◽  
Charge Loss ◽  
Capacitance Voltage ◽  
Nitride Oxide ◽  
N2 Plasma

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N2 plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N2 plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed.

scholarly journals Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1401
Author(s):  
Jun-Kyo Jeong ◽  
Jae-Young Sung ◽  
Woon-San Ko ◽  
Ki-Ryung Nam ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Memory Performance ◽  
Charge Trapping ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Retention ◽  
Threshold Voltage Shift ◽  
Before And After ◽  
Nitride Oxide

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

Polycrystalline Silocon-Oxide-Nitride-Oxide-Silicon Flash Memory on SiO2 and Si3N4 Buffer Layer for System on Panels Application

2013 ◽  
Vol 658 ◽  
pp. 120-123
Author(s):  
Sang Youl Lee ◽  
Jae Sub Oh ◽  
Seung Dong Yang ◽  
Ho Jin Yun ◽  
Kwang Seok Jeong ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Buffer Layer ◽  
Flash Memory ◽  
Polycrystalline Silicon ◽  
Silicon Oxide ◽  
Memory Device ◽  
Nitride Layer ◽  
X Ray Diffraction ◽  
X Ray ◽  
Nitride Oxide

For the system on panel applications, we fabricated and analyzed the polycrystalline silicon (poly-Si) silicon-oxide-nitride-oxide-silicon (SONOS) memory device on different buffer layer such as oxide or nitride. The threshold voltage (VT) and transconductance (gm) are extracted from each device and the X-Ray Diffraction (XRD) measurement is carried out to interpret these characteristics. The results show the device on oxide layer has higher mobility and lower VT than on nitride layer. From the XRD spectra, it can be explained by the fact that the grain size of poly-Si on oxide layer has larger than on nitride layer. The both devices show program/erase characteristics as the potential of SOP memory devices.

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