Thermal Stress Behavior of Aluminum Nanofilms under Heat Cycling

2004 ◽  
Author(s):  
Kazuya Kusaka
2008 ◽  
Author(s):  
T. Hanabusa ◽  
M. Nishida ◽  
K. Kusaka ◽  
Abarrul Ikram ◽  
Agus Purwanto ◽  
...  

2013 ◽  
Vol 2013.19 (0) ◽  
pp. 565-566
Author(s):  
Ryouta Numaguchi ◽  
Akira Chiba ◽  
Souta Matsusaka ◽  
Hirofumi Hidai ◽  
Noboru Morita

2006 ◽  
Vol 20 (25n27) ◽  
pp. 4691-4696 ◽  
Author(s):  
TAKAO HANABUSA ◽  
KAZUYA KUSAKA ◽  
SHOSO SHINGUBARA ◽  
OSAMI SAKATA

In-situ observation of thermal stresses in thin films deposited on a silicon substrate was made by synchrotron radiation. Specimens prepared in this experiment were nano-size thin aluminum films with SiO 2 passivation. The thickness of the films was 10 nm, 20 nm and 50 nm. Synchrotron radiation revealed the diffraction intensities for these thin films and make possible to measure stresses in nano-size thin films. Residual stresses in the as-deposited state were tensile. Compressive stresses were developed in a heating cycle up to 300°C and tensile stresses were developed in a cooling cycle. The thermal stresses in the 50 nm film showed linear behavior in the first heating stage from room temperature to 250°C followed by no change in the stress at 300°C, however, linearly behaved in the second cycle. On the other hand, the thermal stresses in 20 nm and 10 nm films almost linearly behaved without any hysteresis in increasing and decreasing temperature cycles. The mechanism of thermal stress behavior in thin films can be explained by strengthening of the nano-size thin films due to inhibition of dislocation source and dislocation motion.


1989 ◽  
Vol 38 (429) ◽  
pp. 623-629 ◽  
Author(s):  
Yasukazu IKEUCHI ◽  
Takao HANABUSA ◽  
Haruo FUJIWARA

2020 ◽  
Vol 305 ◽  
pp. 198-206
Author(s):  
Yuan Ping Luh ◽  
Jia Fu Jhang ◽  
Huang Li Wang ◽  
Fu Haw Yu ◽  
Chang Hung Tu

Electronic products have been following light, thin, short, small as goals. In recent years, not only do these features have to provide more functionality and reliability. In response to this demand, many new processes such as wafer-level 7 nm euv and electronic packaging solutions have been developed in the market. Stacked wafer technology has been widely used in electronic packaging solutions in a variety of storage devices and electronic products. The accompanying problems and challenges continue to emerge, in which the delamination of the package failure mode leads to the inability of electronic products to operate as the biggest issue. This study is mainly to investigate the thermal stress behavior of the vertical stacking of chip bonds of wafer adhesives to reduce the thickness of the wafer in the stacked wafer structure to Improve package reliability by reducing the amount of deformation Utilize one-half symmetry model and adopt the reflow profile of JESD22-a113 (25 °C ~ 260 °C) As a basis and import into the ansys software for parametric development, Then use the Taguchi experiment method to configure the experimental parameters to explore the optimization parameters. Finally, the experimental results and the delamination results were verified by the Taguchi experiment method, and the stress shrinkage gradient model was introduced to find the next best potential factor for reducing the maximum stress, such as binder material Tg and Young's modulus compensation thermal expansion system. Observe the thermal stress behavior of stacked chips and help provide a reference for providing modified changes during development.


2009 ◽  
Vol 145-146 ◽  
pp. 211-214 ◽  
Author(s):  
Yi Wei Chen ◽  
Nien Ting Ho ◽  
Jerander Lai ◽  
T.C. Tsai ◽  
C.C. Huang ◽  
...  

NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.


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