Miniaturized impression creep testing of ball grid array solder balls attached to microelectronic packaging substrates

2004 ◽  
Vol 75 (12) ◽  
pp. 5244-5252 ◽  
Author(s):  
D. Pan ◽  
R. A. Marks ◽  
I. Dutta ◽  
R. Mahajan ◽  
S. G. Jadhav
Keyword(s):  
Ball Grid Array ◽  
Creep Testing ◽  
Microelectronic Packaging ◽  
Impression Creep ◽  
Solder Balls

Creep Behavior of Lead Free Solder Interconnects in Microelectronic Packages: Impression Creep Testing and Constitutive Modeling

2005 ◽  
Author(s):  
I. Dutta ◽  
D. Pan ◽  
S. Jadhav ◽  
R. Mahajan
Keyword(s):  
Creep Behavior ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Creep Testing ◽  
Lead Free ◽  
Creep Model ◽  
Impression Creep ◽  
Creep Response ◽  
Microelectronic Packages ◽  
Free Solder

The creep behavior of ball grid array (BGA) or flip-chip (FC) solder joints during thermo-mechanical cycling associated with service often limits the reliability of microelectronic packages. In addition, the fine intermetallic precipitates (Ag3Sn and/or Cu6Sn5) in the microstructures of the new lead-free solders (Sn-Ag and Sn-Ag-Cu) can undergo significant in situ strain-enhanced coarsening during TMC, resulting in in-service evolution of the creep behavior of the joints. Since there are significant microstructural/ compositional differences between bulk solder samples and tiny microelectronic solder joints, it is critical to develop accurate creep testing methodologies on tiny life-sized solder joints and microstructurally adaptive constitutive creep models for the emerging Pb-free solder alloys. In this paper, we present creep data obtained from tests conducted on individual Sn4Ag0.5Cu ball grid array (BGA) solder balls attached to a packaging substrate, using a newly developed miniaturized impression creep apparatus, which affords high test throughput with minimal sample preparation. Coarsening of intermetallic particles is demonstrated to influence creep behavior in two ways. At low stresses, the creep rate increases proportionately with precipitate size. At high stresses, precipitate coarsening influences creep response by altering the threshold stress for particle-limited creep. Based on the experimental observations, a microstructurally adaptive creep model, which accounts for the effects of coarsening on the creep response of solder joints, and is capable of adjusting itself as solder joint microstructures evolve during service, is presented, along with experimental determination of the relevant coarsening kinetics parameters.

A 10 MHz to 80 GHz BGA Transition from Chip to LTCC Interposer for Chip Scale Packages

2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000067-000072
Author(s):  
Bradley A. Thrasher ◽  
William E. McKinzie ◽  
Deepukumar M. Nair ◽  
Michael A. Smith ◽  
Allan Beikmohamadi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Electrical Performance ◽  
60 Ghz ◽  
Test Chip ◽  
Full Wave ◽  
Test Board ◽  
Measurement Results ◽  
Solder Balls

Presented here are the design, fabrication, and measurement results of a low temperature cofired ceramic (LTCC) chip-to-interposer transition utilizing a flip-chip ball grid array (BGA) interconnect that provides excellent electrical performance up to and including 80 GHz. A test board fabricated in LTCC is used as the interposer substrate and another smaller LTCC part is used as a surrogate chip for demonstration purposes. The BGA chip-to-interposer transition is designed as a back-to-back pair of transitions with an assembly consisting of an LTCC interposer, an LTCC test chip, and a BGA interconnect constructed with 260 μm diameter polymer core solder balls. The LTCC material employed is DuPont™ GreenTape™ 9K7. Full-wave simulation results predict excellent electrical performance from 10 MHz to 80 GHz, with the chip-to-interposer BGA transition having less than 0.5 dB insertion loss at 60 GHz and less than 1 dB insertion loss up to 80 GHz. In an assembled package (back-to-back BGA transitions), the insertion loss was measured to be 1 dB per transition at 60 GHz and less than 2 dB per transition for all frequencies up to 80 GHz.

Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000112-000116
Author(s):  
Joelle Arnold ◽  
Steph Gulbrandsen ◽  
Nathan Blattau
Keyword(s):  
Computer Tomography ◽  
Damage Accumulation ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Acoustic Microscopy ◽  
Eutectic Solder ◽  
X Ray ◽  
Area Array ◽  
Solder Balls ◽  
Commercial Off The Shelf

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.

Robust Design Optimization of Ball Grid Array Packaging

2011 ◽  
Author(s):  
Jae Chang Kim ◽  
Joo-Ho Choi ◽  
Yeong K. Kim
Keyword(s):  
Design Optimization ◽  
Robust Design ◽  
Strain Energy ◽  
Reduction Method ◽  
Ball Grid Array ◽  
Robust Design Optimization ◽  
Molding Compound ◽  
Materials Modeling ◽  
Solder Balls ◽  
Input Variables

In this paper, comparisons of the design optimization of ball grid array packaging geometry based on the elastic and viscoelastic material properties are made. Six geometric dimensions of the packaging are chosen as input variables. Molding compound and substrate are modeled as elastic and viscoelastic, respectively. Viscoplastic finite element analyses are performed to calculate the strain energy densities (SED) of the eutectic solder balls. Robust design optimizations to minimize SED are carried out, which accounts for the variance of the parameters via Kriging dimension reduction method. Optimum solutions are compared with those by the Taguchi method. It is found that the effects of the packaging geometry on the solder ball reliability are significant, and the optimization results are different depending on the materials modeling.

Electrical resistance of Sn–Ag–Cu ball grid array packages with Sn–Zn–Bi addition jointed at 240 °C

2007 ◽  
Vol 22 (1) ◽  
pp. 113-123
Author(s):  
Po-Cheng Shih ◽  
Kwang-Lung Lin
Keyword(s):  
Control System ◽  
Intermetallic Compound ◽  
Aging Time ◽  
Electrical Resistance ◽  
Ball Grid Array ◽  
Solder Paste ◽  
Solder Balls ◽  
Solder Bulk ◽  
Ball Grid Array Packages

Sn–8Zn–3Bi solder paste and Sn–3.2Ag–0.5Cu solder balls were reflowed simultaneously at 240 °C on Cu/Ni/Au metallized ball grid array substrates. The joints without Sn–Zn–Bi addition (only Sn–Ag–Cu) were studied as a control system. Electrical resistance was measured after multiple reflows and aging. The electrical resistance of the joint (R1) consisted of three parts: the solder bulk (Rsolder bulk, upper solder highly beyond the mask), interfacial solder/intermetallic compound (Rsolder/IMC), and the substrate (Rsubstrate). R1 increased with reflows and aging time. Rsolder/IMC, rather than Rsolder bulk and Rsubstrate, seemed to increase with reflows and aging time. The increase of R1 was ascribed to the Rsolder/IMC rises. Rsubstrate was the major contribution to R1. However Rsolder/IMC dominated the increase of R1 with reflows and aging. R1 of Sn–Zn–Bi/Sn–Ag–Cu samples were higher than that of Sn–Ag–Cu samples in various tests.

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