Back-side-illuminated high-speed Ge photodetector fabricated on Si substrate using thin SiGe buffer layers

2004 ◽  
Vol 85 (15) ◽  
pp. 3286-3288 ◽  
Author(s):  
Zhihong Huang ◽  
Jungwoo Oh ◽  
Joe C. Campbell
Keyword(s):  
High Speed ◽  
Buffer Layers ◽  
Back Side ◽  
Si Substrate

High-κ Insulator Thin Films and Retention Properties of MFIS Diodes

2011 ◽  
Vol 1345 ◽  
Author(s):  
Yichun Zhou
Keyword(s):  
Thin Films ◽  
Leakage Current ◽  
High Speed ◽  
Random Access ◽  
Ferroelectric Thin Film ◽  
Buffer Layers ◽  
Interface Properties ◽  
Si Substrate ◽  
Device Structure ◽  
Low Leakage

ABSTRACTFerroelectric field effect transistor (FFET) is a promising candidate for non-volatile random access memory because of its high speed, single device structure, low power consumption, and nondestructive read-out operation. Currently, however, such ideal devices are commercially not available due to poor interface properties between ferroelectric film and Si substrate, such as leakage current and interdiffusion etc. So we choose YSZ and HfO2 insulating thin films as buffer layer due to they possess relatively high dielectric constant, high thermal stability, low leakage current, and good interface property with Si substrates. Two structural diodes of Pt/BNT/YSZ/Si and Pt/SBT/HfO2/Si were fabricated, and the microstructures, interface properties, C-V, I-V, and retention properties were investigated in detail. Experimental results show that the fabricated diodes exhibit excellent long-term retention properties, which is due to the good interface and the low leakage density, demonstrating that the YSZ and HfO2 buffer layers are playing a critical modulation role between the ferroelectric thin film and Si substrate.

High-speed-response InGaAs/InP heterostructure avalanche photodiode with InGaAsP buffer layers

1982 ◽  
Vol 18 (22) ◽  
pp. 945 ◽  
Author(s):  
Y. Matsushima ◽  
S. Akiba ◽  
K. Sakai ◽  
Y. Kushiro ◽  
Y. Noda ◽  
...  
Keyword(s):  
High Speed ◽  
Avalanche Photodiode ◽  
Buffer Layers ◽  
Speed Response

Electron Traps in n-GaN Grown on Si (111) Substrates by MOVPE

2008 ◽  
Vol 1068 ◽  
Author(s):  
Tsuneo Ito ◽  
Yutaka Terada ◽  
Takashi Egawa
Keyword(s):  
Sapphire Substrate ◽  
Deep Level ◽  
Buffer Layers ◽  
Si Substrate ◽  
Electron Traps ◽  
Organic Vapor ◽  
Pair Number ◽  
Metal Organic ◽  
Transient Spectroscopy ◽  
Gan On Si

ABSTRACTDeep level electron traps in n-GaN grown by metal organic vapor phase epitaxy (MOVPE) on Si (111) substrate were studied by means of deep level transient spectroscopy (DLTS). The growth of n-GaN on different pair number of AlN/GaN superlattice buffer layers (SLS) system and on c-face sapphire substrate are compared. Three deep electron traps labeled E4 (0.7-0.8 eV), E5 (1.0-1.1 eV), were observed in n-GaN on Si substrate. And the concentrations of these traps observed for n-GaN on Si are very different from that on sapphire substrate. E4 is the dominant of these levels for n-GaN on Si substrate, and it behaves like point-defect due to based on the analysis by electron capture kinetics, in spite of having high dislocation density of the order of 1010 cm−3.

Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

2000 ◽  
Vol 640 ◽  
Author(s):  
Nabil Sghaier ◽  
Abdel K. Souifi ◽  
Jean-Marie Bluet ◽  
Manuel Berenguer ◽  
Gérard Guillot ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Frequency Dispersion ◽  
Buffer Layers ◽  
Si Substrate ◽  
Substrate Interface ◽  
Si Substrates ◽  
Kink Effect ◽  
Parasitic Effect ◽  
Output Characteristics ◽  
Output Conductance

ABSTRACTThe aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

Growth of zinc blende GaAs/AlGaAs heterostructure nanowires on Si substrate by using AlGaAs buffer layers

2012 ◽  
Vol 359 ◽  
pp. 30-34 ◽  
Author(s):  
Jingwei Guo ◽  
Hui Huang ◽  
Yizheng Ding ◽  
Zhuoyu Ji ◽  
Ming Liu ◽  
...  
Keyword(s):  
Buffer Layers ◽  
Si Substrate ◽  
Zinc Blende

Preparation of Textured Growth Pb(Zr,Ti)O3 Thin Films on Si Substrate Using SrTiO3 as Buffer Layers

2003 ◽  
Vol 57 (1) ◽  
pp. 1257-1264 ◽  
Author(s):  
Chien-Kang Kao ◽  
Niranjan Prakash Kuraganti ◽  
Chuen-Horng Tsai ◽  
I-Nan Lin ◽  
Rajendra Kumar Pandey ◽  
...  
Keyword(s):  
Thin Films ◽  
Buffer Layers ◽  
Si Substrate

AlGaAs/InGaAs High Electron Mobility Transistor Grown on Si Substrate with Ge/GexSi1-xMetamorphic Buffer Layers

2008 ◽  
Vol 47 (9) ◽  
pp. 7069-7072 ◽  
Author(s):  
Edward Yi Chang ◽  
Jui-Chien Huang ◽  
Yueh-Chin Lin ◽  
Yen-Chang Hsieh ◽  
Chia-Yuan Chang
Keyword(s):  
Electron Mobility ◽  
High Electron Mobility Transistor ◽  
Buffer Layers ◽  
High Electron ◽  
Si Substrate ◽  
High Electron Mobility

High quality and high speed cutting of 4H-SiC JFET wafers including PCM structures by using Thermal Laser Separation

2014 ◽  
Vol 1693 ◽  
Author(s):  
Dirk Lewke ◽  
Matthias Koitzsch ◽  
Karl Otto Dohnke ◽  
Martin Schellenberger ◽  
Hans-Ulrich Zuehlke ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Back Side ◽  
The Novel ◽  
Metal Structures ◽  
High Speed Cutting ◽  
Current State ◽  
Current Transition ◽  
First Time ◽  
Laser Separation

ABSTRACTThe silicon carbide (SiC) market is gaining momentum hence productivity in device manufacturing has to be improved. The current transition from 100 mm SiC-wafers to 150 mm SiC-wafers requires novel processes in the front-end as well as the back-end of SiC-chip production. Dicing of fully processed SiC-wafers is becoming a bottleneck process since current state-of-the-art mechanical blade dicing faces heavy tool wear and achieves low throughput due to low feed rates in the range of only a few mm/s. This paper presents latest results of the novel dicing technology Thermal Laser Separation (TLS) applied for separating SiC-JFETs. We demonstrate for the first time that TLS is capable of dicing fully processed 4H-SiC wafers, including back side metal layer stacks, process control monitoring (PCM), and metal structures inside the dicing streets with feed rates up to 200 mm/s. TLS thus paves the way to efficient dicing of 150 mm SiC-wafers.

Investigation on the Heat Conduction in Si/3C-SiC/Graphene Film

2014 ◽  
Vol 487 ◽  
pp. 63-66
Author(s):  
Zan Wang ◽  
Hua Wei Guan
Keyword(s):  
Molecular Dynamics ◽  
Heat Conduction ◽  
Composite Films ◽  
Graphene Film ◽  
Buffer Layers ◽  
Nonequilibrium Molecular Dynamics ◽  
Interfacial Thermal Resistance ◽  
Si Substrate ◽  
Maximum Value ◽  
Dynamics Method

Based on the nonequilibrium Molecular Dynamics method, interfacial thermal resistances of Si/3C-SiC/grphene composite films are investigated. The dependencies of interfacial thermal resistances of Si/3C-SiC and 3C-SiC/grphene on temperatures and the thickness of buffer layers are simulated separately. The results indicate that the interfacial thermal resistances of Si/3C-SiC and 3C-SiC/grphene increase with the increase of temperatures at the range of 100~700K, and converge to 3.4×10-9 Km2/W. In the Si/3C-SiC/grphene composite film, 3C-SiC connects Si substrate with grphene sheets. The results show the relationships between interfacial thermal resistances and the thickness are not prominent, and the maximum value of interfacial thermal resistance locates at 24×3.35 Å.

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