Electrical activation in silicon-on-insulator after low energy boron implantation

2004 ◽  
Vol 96 (4) ◽  
pp. 1891-1898 ◽  
Author(s):  
Antonio F. Saavedra ◽  
Kevin S. Jones ◽  
Mark E. Law ◽  
Kevin K. Chan ◽  
Erin C. Jones
Keyword(s):  
Low Energy ◽  
Silicon On Insulator ◽  
Electrical Activation ◽  
Boron Implantation

Characterisation of Low Energy Boron Implantation and Fast Ramp-Up Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
E. J. H. Collart ◽  
G. de Cock ◽  
A. J. Murrell ◽  
M. A. Foad
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Low Energy ◽  
Electrical Activation ◽  
Junction Depth ◽  
Boron Implantation

ABSTRACTThe effects of ramp-up rate during rapid thermal processing of ultra-shallow boron implants have been investigated. Ramp-up rates were varied between 25 °C and 200 °C for two types of anneals: soak anneals and spike anneals. It was found that the ramp-up rate had very little influence on junction depth or electrical activation for both types of anneals. Spike anneals did produce shallower profiles than soak anneal for a comparable electrical activation and may be an option for future processes.

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

Electrical activation of arsenic implanted in silicon on insulator (SOI)

2007 ◽  
Vol 40 (17) ◽  
pp. 5227-5231 ◽  
Author(s):  
R M de Oliveira ◽  
M Dalponte ◽  
H Boudinov
Keyword(s):  
Silicon On Insulator ◽  
Electrical Activation

Low energy boron implantation profiles in silicon from junction depth measurements

1971 ◽  
Vol 7 (1-2) ◽  
pp. 7-15 ◽  
Author(s):  
P. Sebillotte ◽  
M. Badanoiu ◽  
V. B. Ndocko ◽  
P. Siffert
Keyword(s):  
Low Energy ◽  
Junction Depth ◽  
Boron Implantation

On the Formation of Ultrathin Simox Structures by Low Energy Implantation

1992 ◽  
Vol 284 ◽  
Author(s):  
F. Namavar ◽  
B. Buchanan ◽  
N. M. Kalkhoran
Keyword(s):  
Integrated Circuits ◽  
Substrate Material ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Great Promise ◽  
Ultrathin Layers ◽  
Commercial Applications ◽  
Competitive Substrate ◽  
The Cost ◽  
Radiation Hard

ABSTRACTSilicon-on-insulator (SOI) wafers made by standard energy (150–200 keV) Separation by IMplantation of Oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. However, if SIMOX material is to become a competitive substrate material for manufacturing commercial integrated circuits, the cost of the SIMOX wafers must be greatly reduced. The low energy SIMOX (LES) process accomplishes the needed reduction in cost by producing ultrathin layers which require much lower ion doses. These ultrathin layers are necessary for the next generation of commercial ultra high density CMOS integrated circuits, and must be of very high quality to be utilized for commercial applications. In this paper we discuss characterization of ultrathin LES structures.

Low energy boron implantation in silicon and room temperature diffusion

1998 ◽  
Vol 139 (1-4) ◽  
pp. 98-107 ◽  
Author(s):  
E.J.H Collart ◽  
K Weemers ◽  
N.E.B Cowern ◽  
J Politiek ◽  
P.H.L Bancken ◽  
...  
Keyword(s):  
Room Temperature ◽  
Low Energy ◽  
Temperature Diffusion ◽  
Boron Implantation

Strain Relaxation in SiGe Thin Films Studied by Low-Energy Electron Microscopy

2001 ◽  
Vol 696 ◽  
Author(s):  
A.R. Woll ◽  
P. Moran ◽  
E.M. Rehder ◽  
B. Yang ◽  
T.F. Kuech ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Strain Relaxation ◽  
Surface Cleaning ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Surface Strain ◽  
Energy Electron ◽  
High Temperature Annealing ◽  
Low Energy Electron ◽  
Dislocation Multiplication

AbstractWe demonstrate the use of low-energy electron microscopy (LEEM) as a tool for studying dis-location formation in low-Ge-content SiGe films on Si(001) and silicon-on-insulator. Compared to TEM, sample preparation for LEEM consists only of conventional surface cleaning. Yet, because of its sensitivity to local variations in surface strain on Si(001), LEEM can detect dislocations at the earliest stages of strain relaxation. In identically prepared SiGe films, the typical dislocation extends over the entire viewable region of several hundred microns in SiGe/Si, but is less than 100 microns in SiGe/SOI. In addition, dislocation cross-slip and threading segments are common in SiGe/SOI, but virtually non-existent in SiGe/Si. We have also observed dislocation formation in real-time during high temperature annealing. Preliminary results appear to demonstrate dislocation multiplication and blocking at a perpendicular glide plane. The applicability of LEEM to strain relaxation in other Si-based systems will be discussed.

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