Publisher’s Note: “Stress-induced effects on depletion-layer capacitance of metal–oxide–semiconductor capacitors” [Appl. Phys. Lett. 83, 4351 (2003)]

2004 ◽  
Vol 84 (2) ◽  
pp. 308-308 ◽  
Author(s):  
Kazunori Matsuda ◽  
Yozo Kanda
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Depletion Layer ◽  
Oxide Semiconductor

Depletion layer formation rate at T<30 °K in buried channel, metal‐oxide‐semiconductor transistors

1984 ◽  
Vol 56 (2) ◽  
pp. 517-521 ◽  
Author(s):  
S. K. Tewksbury ◽  
M. R. Biazzo ◽  
T. L. Lindstrom ◽  
D. M. Tennant
Keyword(s):  
Metal Oxide ◽  
Formation Rate ◽  
Metal Oxide Semiconductor ◽  
Depletion Layer ◽  
Oxide Semiconductor ◽  
Layer Formation ◽  
Buried Channel

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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