Modeling of gate-induced drain leakage current in n-type metal–oxide–semiconductor field effect transistor

2001 ◽  
Vol 89 (3) ◽  
pp. 1880 ◽  
Author(s):  
A. Touhami ◽  
A. Bouhdada
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor

POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT

2014 ◽  
Vol 23 (08) ◽  
pp. 1450109
Author(s):  
K. KEERTI KUMAR ◽  
N. BHEEMA RAO
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Nand Gate ◽  
Power Gating ◽  
Cmos Inverter ◽  
Effect Transistor

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

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