Microscopic lock-in thermography investigation of leakage sites in integrated circuits

2000 ◽  
Vol 71 (11) ◽  
pp. 4155 ◽  
Author(s):  
O. Breitenstein ◽  
M. Langenkamp ◽  
F. Altmann ◽  
D. Katzer ◽  
A. Lindner ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Lock In

scholarly journals New Developments in IR Lock-In Thermography

2004 ◽  
Author(s):  
O. Breitenstein ◽  
J.P. Rakotoniaina ◽  
M. Hejjo Al Rifai ◽  
M. Gradhand ◽  
F. Altmann ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Spatial Resolution ◽  
Infrared Camera ◽  
Detection Sensitivity ◽  
New Developments ◽  
Technical Developments ◽  
Corrected Image ◽  
Lock In ◽  
Blurring Effect ◽  
Colloidal Bismuth

Abstract Lock-in thermography based on an infrared camera has proven to be a useful tool for failure analysis of integrated circuits (ICs). This article discusses four novel technical developments of lock-in thermography. These developments are blackening the IC surface with colloidal bismuth, the synchronous undersampling technique allowing the use of higher lock-in frequencies, displaying the 0deg/-90deg signal as a novel high resolution emissivity corrected image type, and removing the thermal blurring effect by mathematically deconvoluting the 0deg/-90deg; signal. The effect of these techniques is demonstrated by using a regularly working operational amplifier (pA 741) and a damaged capacitor as test devices. It is shown that blackening the IC surface improves the detection sensitivity in metallized regions by up to a factor of 10, whereas the other methods allow improvement of the effective spatial resolution. The article also discusses which of the spatial resolution improvement techniques is most appropriate in different situations.

Correlation of Thermal Rise Time to Sample Depth in Multi-Die Stacked Devices

2018 ◽  
Author(s):  
M. Shi ◽  
A.G. Street ◽  
Y.F. Dai
Keyword(s):  
Integrated Circuits ◽  
Rise Time ◽  
Thermal Source ◽  
Memory Devices ◽  
Digital Modulation ◽  
Sample Depth ◽  
Lock In ◽  
Thermal Sources ◽  
Stacked Memory

Abstract Dynamic Digital Modulation, an adaptation of Lock-In Thermography, has been shown to be a useful technique to establish the relative Z-depth of thermal sources in integrated circuits. In order to determine the specific depth of a thermal source it is necessary to correlate known depths to measured thermal rise time. In this work, multi-die stacked memory devices are used as calibration sources to correlate a thermal source at individual die to the measured thermal rise time.

Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission

2019 ◽  
Author(s):  
Paul Hubert P. Llamera ◽  
Camille Joyce G. Garcia-Awitan
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Near Infrared ◽  
Thermal Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
Distinct Advantage ◽  
Infra Red ◽  
Emission Microscopy ◽  
Lock In

Abstract Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

scholarly journals Heterodyne lock-in thermal coupling measurements in integrated circuits: Applications to test and characterization

2009 ◽  
Vol 80 (2) ◽  
pp. 026101 ◽  
Author(s):  
J. Altet ◽  
E. Aldrete-Vidrio ◽  
D. Mateo ◽  
A. Salhi ◽  
S. Grauby ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Thermal Coupling ◽  
Lock In

Lock-In-Thermography for 3-Dimensional Localization of Electrical Defects inside Complex Packaged Devices

2008 ◽  
Author(s):  
C. Schmidt ◽  
F. Altmann ◽  
C. Grosse ◽  
A. Lindner ◽  
V. Gottschalk
Keyword(s):  
Integrated Circuits ◽  
Hot Spots ◽  
Signal To Noise Ratio ◽  
Thermal Response ◽  
Temperature Fields ◽  
Single Chip ◽  
3 Dimensional ◽  
Lateral Localization ◽  
Lock In ◽  
Non Destructive

Abstract It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

The study of interfacial reactions of nickel thin films on GaAs

1983 ◽  
Vol 41 ◽  
pp. 156-157
Author(s):  
L.J. Chen ◽  
Y.F. Hsieh
Keyword(s):  
Thin Films ◽  
Integrated Circuits ◽  
Interfacial Reactions ◽  
Metal Contacts ◽  
Nickel Thin Films ◽  
Thin Foils ◽  
The Status ◽  
Si Doped ◽  
Electron Microscopes

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

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