Contrast reversal in scanning capacitance microscopy imaging

1998 ◽  
Vol 73 (18) ◽  
pp. 2597-2599 ◽  
Author(s):  
Robert Stephenson ◽  
Anne Verhulst ◽  
Peter De Wolf ◽  
Matty Caymax ◽  
Wilfried Vandervorst
Keyword(s):  
Microscopy Imaging ◽  
Scanning Capacitance Microscopy

Quantification of scanning capacitance microscopy imaging of the pn junction through electrical simulation

1999 ◽  
Vol 74 (2) ◽  
pp. 272-274 ◽  
Author(s):  
M. L. O’Malley ◽  
G. L. Timp ◽  
S. V. Moccio ◽  
J. P. Garno ◽  
R. N. Kleiman
Keyword(s):  
Microscopy Imaging ◽  
Scanning Capacitance Microscopy ◽  
Electrical Simulation ◽  
Pn Junction

Effect of surface oxide characteristics on Scanning Capacitance Microscopy Imaging

1999 ◽  
Vol 5 (S2) ◽  
pp. 978-979
Author(s):  
Atul. A. Konkar ◽  
Wei Chen ◽  
Kari Noehring
Keyword(s):  
Differential Capacitance ◽  
Surface Oxide ◽  
Oxide Semiconductor ◽  
Semiconductor Surface ◽  
High Signal ◽  
Contact Mode ◽  
Microscopy Imaging ◽  
Scanning Capacitance Microscopy ◽  
Mos Structure ◽  
The Difference

Scanning capacitance microscopy (SCM) is currently one of the most promising tools for twodimensional carrier profiling. This technique, based upon atomic force microscope (AFM) operated in the contact mode, uses a conductive probe which is scanned over the semiconductor surface. The conductive probe, oxide on the surface of the semiconductor, and the semiconductor substrate form a metal-oxide-semiconductor (MOS) structure. An a.c. bias is applied to the tip and the capacitance of the MOS structure is monitored. The a.c. bias changes the depletion of carriers in the semiconductor and thus the total capacitance of the structure. The maximum capacitance of the MOS structure is obtained when the semiconductor is in accumulation and the total capacitance of the structure is the capacitance of the semiconductor surface oxide. The minimum capacitance is obtained when the semiconductor region under the tip is in inversion. Since SCM the output signal is proportional to the differential capacitance, to get a high signal we need to maximize the difference between the maximum and minimum in the total MOS capacitance.

Electrical simulation of scanning capacitance microscopy imaging of the pn junction with semiconductor probe tips

1999 ◽  
Vol 74 (24) ◽  
pp. 3672-3674 ◽  
Author(s):  
M. L. O’Malley ◽  
G. L. Timp ◽  
W. Timp ◽  
S. V. Moccio ◽  
J. P. Garno ◽  
...  
Keyword(s):  
Microscopy Imaging ◽  
Scanning Capacitance Microscopy ◽  
Electrical Simulation ◽  
Pn Junction

Low - Voltage Scanning Electron Microscopy Imaging, Secondary and Backscatter, With Microchannel Plate Detector

1990 ◽  
Vol 48 (1) ◽  
pp. 442-442
Author(s):  
Galen Powers ◽  
Ray Cochran
Keyword(s):  
Low Voltage ◽  
Beam Current ◽  
Microchannel Plate ◽  
Normal Operation ◽  
Microscopy Imaging ◽  
Backscatter Signal ◽  
Vacuum Interface ◽  
Width Measurements ◽  
Working Distance ◽  
Beam Currents

The capability to obtain symmetrical images at voltages as low as 200 eV and beam currents less than 9 pico amps is believed to be advantageous for metrology and study of dielectric or biological samples. Symmetrical images should allow more precise and accurate line width measurements than currently achievable by traditional secondary electron detectors. The low voltage and current capability should allow imaging of samples which traditionally have been difficult because of charging or electron beam damage.The detector system consists of a lens mounted dual anode MicroChannel Plate (MCP) detector, vacuum interface, power supplies, and signal conditioning to interface directly to the video card of the SEM. The detector has been miniaturized so that it does not interfere with normal operation of the SEM sample handling and alternate detector operation. Biasing of the detector collection face will either add secondaries to the backscatter signal or reject secondaries yielding only a backscatter image. The dual anode design allows A−B signal processing to provide topological information as well as symmetrical A+B images.Photomicrographs will show some of the system capabilities. Resolution will be documented with gold on carbon. Variation of voltage, beam current, and working distance on dielectric samples such as glass and photoresist will demonstrate effects of common parameter changes.

Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors

2005 ◽  
Author(s):  
M.L. Anderson ◽  
P. Tangyunyong ◽  
T.A. Hill ◽  
C.Y. Nakakura ◽  
T.J. Headley ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
New Product Development ◽  
Yield Enhancement ◽  
Product Development Process ◽  
Product Lines ◽  
Scanning Capacitance Microscopy ◽  
Transmission Electron ◽  
Complementary Techniques ◽  
Analytical Tools

Abstract By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy

2006 ◽  
Author(s):  
J.S. McMurray ◽  
C.M. Molella
Keyword(s):  
The Body ◽  
Silicon On Insulator ◽  
Back Side ◽  
Cross Sectional ◽  
Plan View ◽  
Spreading Resistance ◽  
Scanning Capacitance Microscopy ◽  
Root Cause ◽  
Cross Sectional Imaging ◽  
Active Channel

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

2006 ◽  
Author(s):  
Vinod Narang ◽  
P. Muthu ◽  
J.M. Chin ◽  
Vanissa Lim
Keyword(s):  
Plasma Etching ◽  
Data Interpretation ◽  
Parameters Optimization ◽  
Scanning Capacitance Microscopy ◽  
Microscopy Technique ◽  
Thermal Oxide ◽  
Specific Analysis ◽  
Thin Oxide ◽  
P Type ◽  
Uv Ozone

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

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