Twin formation in As precipitates in low-temperature GaAs during high-temperature annealing

1998 ◽  
Vol 72 (2) ◽  
pp. 226-228 ◽  
Author(s):  
S. Ruvimov ◽  
Ch. Dicker ◽  
J. Washburn ◽  
Z. Liliental-Weber
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
High Temperature Annealing ◽  
Twin Formation ◽  
Low Temperature Gaas

Effect of Low-Temperature Recovery Treatments on Subsequent Recrystallization in Al-2.5%Mg

2007 ◽  
Vol 550 ◽  
pp. 381-386 ◽  
Author(s):  
B. Decreus ◽  
Hatem S. Zurob ◽  
John Dunlop ◽  
Yves Bréchet
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Hardness Measurement ◽  
Optical Metallography ◽  
Mg Alloys ◽  
High Temperature Annealing ◽  
Recrystallization Kinetics ◽  
Temperature Recovery ◽  
Kinetics Of ◽  
And Calorimetry

The effect of low temperature recovery treatments on the recrystallization kinetics during subsequent high temperature annealing was investigated in three Al-2.5%Mg alloys with various Fe additions. Recovery treatments were carried out at 190oC for times ranging from 0.25 to 65 hrs. Recrystallization treatments were carried out at 280oC. The kinetics of recrystallization was followed using the techniques of hardness measurement, optical metallography and calorimetry.

The Template Technique Applied to Epitaxial Growth of CrSi2 on Silicon (111)

1993 ◽  
Vol 317 ◽  
Author(s):  
John E. Manan ◽  
Robert G. Long ◽  
André Vantomme ◽  
Marc-A. Nicolet
Keyword(s):  
Thin Films ◽  
High Temperature ◽  
Low Temperature ◽  
Epitaxial Growth ◽  
Film Formation ◽  
The Other ◽  
High Temperature Annealing ◽  
Growth Technique ◽  
Reactive Deposition ◽  
Chromium Evaporation

ABSTRACTThe template growth technique was applied to the growth of CrSi2 thin films on Si(111) by UHV E-gun evaporation. A 4He+ channeling yield of -50% was obtained for an epitaxial -2100 Å-thick film of continuous morphology grown at 450° C The heteroepitaxial relationship is CrSi2 (001) / Si (lll) with CrSi2[210] ∥ Si<110>.In the case of film formation simply via reactive deposition epitaxy (RDE, chromium evaporation onto hot substrates) a severe crystallinity-Morphology tradeoff is always observed. Continuous films are formed at low temperature but no long-range epitaxy is found. On the other hand, high temperature annealing of these films induces the formation of islands that show good epitaxial alignment with the substrate. This tradeoff was addressed with the template growth technique.

Photoluminescence Studies of Annealed GaAs Films Grown on Si Substrates

1988 ◽  
Vol 116 ◽  
Author(s):  
M. Bugajski ◽  
K. Nauka ◽  
S.J. Rosner ◽  
D. Mars
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Free Carrier ◽  
Apparent Difference ◽  
High Temperature Annealing ◽  
Si Substrates ◽  
Gaas Films ◽  
Excitonic Emission ◽  
Heavily Doped ◽  
Photoluminescence Studies

AbstractLow temperature (T - 5K) photoluminescence (PL) has been measured on a variety of as-grown and annealed GaAs films grown on Si substrates by the MBE technique. The PL spectra of the annealed GaAs layers showed an apparent difference between the nomigally undoped samples with free carrier concentrations below 1015 cm−3 and the layers with dopant concentrations exceeding 1017 atoms cm−3 . The annealing caused an increase of both excitonic and defect related PL intensities in low doped samples. In heavily doped layers the annealing suppressed excitonic emission and strongly enhanced defect related luminescence bands. Observed post annealed infrared shifts of the PL peaks in the excitonic region are explained assuming a tetragonally distorted GaAs lattice under tensile stress, and an increase in stress after high temperature annealing.

Impact of Polycrystalline Silicon Processing on Properties of MOS Memory Devices

1990 ◽  
Vol 182 ◽  
Author(s):  
G. Queirolo ◽  
M. Brambilla ◽  
C. Mavero
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Polycrystalline Silicon ◽  
Breakdown Field ◽  
Memory Devices ◽  
High Temperature Annealing ◽  
High Fluence ◽  
Low Temperature Oxidation ◽  
Temperature Oxidation ◽  
Interpoly Oxide

AbstractIn EEPROMs mèmory devices, tunnel oxides with high fluence, and interpoly oxides with low conductivity and high breakdown field are needed. Tunnel oxide fluence is degraded by high temperature annealing after the polysilicon deposition, while interpoly oxide is degraded by low temperature oxidation, particularly on rough films. As a consequence, a process optimization, giving a good compromise between these two quantities is required. In this work we shown that if a flat polysilicon is used, an interpoly oxide of good quality can be obtained at low temperature, maintaining a high value for the tunnel oxide fluence.

Two Step O2/N2O Plasma Annealing for the Reduction of Leakage Current in Amorphous Ta2O5 Films

1999 ◽  
Vol 567 ◽  
Author(s):  
W.S. Lau ◽  
M.T. Chandima Perera ◽  
T. Han ◽  
N. P. Sandler ◽  
C.H. Tung ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Grain Boundaries ◽  
Leakage Current ◽  
Tantalum Pentoxide ◽  
High Temperature Annealing ◽  
Voltage Range ◽  
Annealing Step ◽  
Current Reduction ◽  
Plasma Annealing

ABSTRACTAs deposited tantalum pentoxide (Ta2O5) films are amorphous. The films will remain amorphous after O2 or N2O plasma annealing at low temperature. High temperature annealing will produce polycrystalline films where grain boundaries can generate leakage current. Previously, we have shown that N2O plasma annealing is superior to O2 plasma annealing in terms of leakage current reduction for AI/Ta2O5/Si capacitors. However, for TiN/Ta2O5/Si capacitors, the leakage current tends to be higher at low bias voltage for N2O plasma annealing compared to O2 plasma annealing. By adding an 02 plasma annealing step and then comparing TiN/Ta2O5/Si capacitors with two step O2/N2O plasma annealing with respect to similar structures with two step O2/O2 plasma annealing, it can be easily seen that TiN/Ta2O5/Si capacitors with two step O2/N2O plasma annealing have lower leakage current compared to similar structures with two step O2/O2 plasma annealing throughtout the voltage range tested.

Evolution of D1-Defect Center in 4H-SiC during High Temperature Annealing

2008 ◽  
Vol 600-603 ◽  
pp. 429-432
Author(s):  
Serguei I. Maximenko ◽  
Jaime A. Freitas ◽  
N.Y. Garces ◽  
E.R. Glaser ◽  
Mark A. Fanton
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Cooling Rate ◽  
Lattice Defects ◽  
High Temperature Annealing ◽  
Defect Center ◽  
Native Defects ◽  
Post Annealing ◽  
Optical Signature ◽  
Low Temperature Photoluminescence

The behavior of the D1 center in semi-insulating 4H-SiC substrates revealed by low-temperature photoluminescence was investigated after post-growth high temperature anneals between 1400 and 2400oC. The influence of different post-anneal cooling rates was also studied. The optical signature of D1 was observed up to 2400oC with intensity maxima at 1700 and 2200oC. We propose that the peak at 1700°C can be related to the formation and subsequent dissociation of SiC native defects. It was found that changes in the post-annealing cooling rate drastically influence the behavior of the D1 center and the concentrations of the VC, VSi, VC-VSi and VC-CSi lattice defects.

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