Totally relaxed GexSi1−xlayers with low threading dislocation densities grown on Si substrates

1991 ◽  
Vol 59 (7) ◽  
pp. 811-813 ◽  
Author(s):  
E. A. Fitzgerald ◽  
Y.‐H. Xie ◽  
M. L. Green ◽  
D. Brasen ◽  
A. R. Kortan ◽  
...  
Keyword(s):  
Threading Dislocation ◽  
Si Substrates ◽  
Dislocation Densities

Strategies For Direct Monolithic Integration of AlxGa(1−x)As/InxGa(1−x)As LEDS and Lasers On Ge/GeSi/Si Substrates Via Relaxed Graded GexSi(1−x) Buffer Layers

2001 ◽  
Vol 692 ◽  
Author(s):  
Michael E. Groenert ◽  
Christopher W. Leitz ◽  
Arthur J. Pitera ◽  
Vicky K. Yang ◽  
Harry Lee ◽  
...  
Keyword(s):  
Chemical Vapor ◽  
Threshold Current ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Carrier Lifetimes ◽  
Si Substrates ◽  
Dislocation Densities ◽  
Minority Carrier Lifetimes ◽  
Current Densities ◽  
High Series

AbstractAlxGa(1−x)As/GaAs quantum well lasers have been demonstrated via organometallic chemical vapor deposition (OMCVD) on relaxed graded GexSi(1−x) virtual substrates on Si. Despite unoptimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities as low as 2×106 cm−2 enabled cw room-temperature lasing at a wavelength of 858nm. The laser structures are oxide-stripe gain-guided devices with differential quantum efficiencies of 0.16 and threshold current densities of 1550A/cm2. Identical devices grown on commercial GaAs substrates showed differential quantum efficiencies of 0.14 and threshold current densities of 1700A/cm2. This comparative data agrees with our previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si substrates. A number of GaAs/Ge/Si integration issues including thermal expansion mismatch and Ge autodoping behavior in GaAs were overcome.

Threading Dislocation Densities in GaAs Grown on Reduced Area Si Substrates

1993 ◽  
Vol 308 ◽  
Author(s):  
J. Knall ◽  
L.T. Romano ◽  
D.K. Biegelsen ◽  
R.D. Bringans
Keyword(s):  
Side Wall ◽  
Heat Treatments ◽  
Threading Dislocation ◽  
Large Area ◽  
Plan View ◽  
Si Substrates ◽  
Gaas On Si ◽  
Dislocation Densities ◽  
Side Walls ◽  
Wall Growth

ABSTRACTWe have studied the possibilities of reducing the threading dislocation (TD) density in GaAs on Si using free side wall growth on patterned Si substrates and/or using a soft ZnSe interlayer in combination with post growth annealing procedures. TD densities were accurately determined using large area plan view TEM and were found to be unaffected by proximity to free side walls and by the ZnSe interlayer. Post growth heat treatments led to a factor of ∼2 reduction in TD density and to bunching of dislocations throughout the thickness of the film.

Reduction of Defect Density in Heteroepitaxial GexSi1-x Grown on Patterned Si Substrates

1989 ◽  
Vol 160 ◽  
Author(s):  
E.A. Fitzgerald ◽  
Y.-H. Xie ◽  
J. Michel ◽  
P.E. Freeland ◽  
B.E. Weir
Keyword(s):  
Defect Density ◽  
Threading Dislocation ◽  
Patterned Substrate ◽  
Si Substrates ◽  
Molecular Beam Epitaxial ◽  
Etch Pit ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Electron Beam Induced Current ◽  
Molecular Beam Epitaxial Growth

AbstractWe have investigated the molecular beam epitaxial growth of GexSi1-x on small growth areas patterned in Si substrates. Electron beam induced current, etch-pit density measurements, transmission electron microscopy, and photoluminescence were used to compare dislocation densities in GexSi1-x on patterned and unpattemed substrates. We find a dramatic reduction in both misfit and threading dislocation densities for the patterned substrate growth. Our results also show that dislocation introduction is dominated by heterogeneous nucleation.

Strain-Free GexSi1−x Layers with Low Threading Dislocation Densities Grown on Si Substrates

1991 ◽  
Vol 220 ◽  
Author(s):  
E. A. Fitzgerald ◽  
Y. H. Xie ◽  
M. L. Green ◽  
D. Brasen ◽  
A. R. Kortan ◽  
...  
Keyword(s):  
Threading Dislocation ◽  
Plan View ◽  
Light Emitting ◽  
Si Substrates ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Electron Beam Induced Current ◽  
Current Densities ◽  
Dimensional Electron Gas ◽  
Compositional Grading

ABSTRACTWe have grown linearly compositionally graded GexSi1−x structures at high temperatures (700–900°C) on Si substrates to form a surface which resembles a GexSi1−x substrate. We have obtained completely relaxed structures with x≤0.50 and threading dislocation densities in the 105cm−2 - 106cm−2 range. Because of the very low threading dislocation densities, the structures appear dislocation free in conventional transmission electron microscopy (TEM) cross-section and plan view. Employing the electron beam induced current technique (EBIC), we were able to consistently measure these low threading dislocation densities. A direct comparison of two x=0.35 films, one graded in Ge content and one uniform in Ge content, shows that compositional grading decreases the dislocation density by a factor of 100–1000. These. higher quality graded buffers have been used as templates for the subsequent growth of InGaP light emitting diodes (LED) and GexSi1−x/Si two-dimensional electron gas (2DEG) structures. Room temperature operation of orange-red LEDs were obtained at current densities of =600A/cm, and mobilities as high as 96,000 cm2/V-s were achieved at 4.2K in the 2DEG structures.

Optimization of SiGe Graded Buffer Defectivity and Throughput by Means of High Growth Temperature and Pre-Threaded Substrates

2005 ◽  
Vol 891 ◽  
Author(s):  
Matthew Erdtmann ◽  
Matthew T. Currie ◽  
Joseph C. Woicik ◽  
David Black
Keyword(s):  
Growth Temperature ◽  
High Growth ◽  
Dislocation Nucleation ◽  
Threading Dislocation ◽  
Threading Dislocations ◽  
Trade Off ◽  
Dislocation Glide ◽  
Si Substrates ◽  
High Growth Temperature ◽  
Dislocation Densities

ABSTRACTDislocation glide kinetics dictate in relaxed graded buffers a fundamental opposition between the defectivity and throughput. For state-of-the-art Si-based applications, the trade-off between defect level and wafer cost (inversely related to throughput) has made the insertion of SiGe graded buffers into production difficult. We aim to mitigate the trade-off by reporting two advances that enable simultaneous improvements in both defectivity and throughput. The first is use of a high growth temperature to allow very fast dislocation glide velocities and growth rates as high as 1.0 μm/min. The second is the use of “pre-threaded” Si substrates, substrates with an elevated density of threading dislocations. By having dislocation nucleation controlled by uniformly distributed substrate threading dislocations, instead of unpredictable heterogeneous sources, impediments to dislocation glide, such as dislocation bundles and pile-ups, are reduced. By incorporating both advances into SiGe graded buffer epitaxy, dislocation pile-up densities are reduced by nearly three orders of magnitude, threading dislocation densities are reduced by a factor of 7.4×, and wafer throughput is increased at least 33%.

Influence of MBE Growth Conditions on Dislocation Densities of GaAs/Ge Epilayers Grown on Silicon Substrates

1985 ◽  
Vol 43 ◽  
pp. 364-365
Author(s):  
K.M. Hones ◽  
P. Sheldon ◽  
B.G. Yacobi ◽  
A. Mason
Keyword(s):  
High Efficiency ◽  
Lattice Mismatch ◽  
Low Cost ◽  
Growth Conditions ◽  
Nonradiative Recombination ◽  
Device Structure ◽  
Si Substrates ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Dislocation Type

There is increasing interest in growing epitaxial GaAs on Si substrates. Such a device structure would allow low-cost substrates to be used for high-efficiency cascade- junction solar cells. However, high-defect densities may result from the large lattice mismatch (∼4%) between the GaAs epilayer and the silicon substrate. These defects can act as nonradiative recombination centers that can degrade the optical and electrical properties of the epitaxially grown GaAs. For this reason, it is important to optimize epilayer growth conditions in order to minimize resulting dislocation densities. The purpose of this paper is to provide an indication of the quality of the epitaxially grown GaAs layers by using transmission electron microscopy (TEM) to examine dislocation type and density as a function of various growth conditions. In this study an intermediate Ge layer was used to avoid nucleation difficulties observed for GaAs growth directly on Si substrates. GaAs/Ge epilayers were grown by molecular beam epitaxy (MBE) on Si substrates in a manner similar to that described previously.

Defect-Engineered Graded GexSi1-x Buffers on Si (001) with Extreme Low Threading Dislocation Density

1995 ◽  
Vol 378 ◽  
Author(s):  
G. Kissinger ◽  
T. Morgenstern ◽  
G. Morgenstern ◽  
H. B. Erzgräber ◽  
H. Richter
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Atomic Force Microscopy ◽  
Dislocation Density ◽  
Threading Dislocation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Threading Dislocation Density

AbstractStepwise equilibrated graded GexSii-x (x≤0.2) buffers with threading dislocation densities between 102 and 103 cm−2 on the whole area of 4 inch silicon wafers were grown and studied by transmission electron microscopy, defect etching, atomic force microscopy and photoluminescence spectroscopy.

High Quality AlN Layer Grown on Patterned Sapphire Substrates by Hydride Vapor-Phase Epitaxy: A Route for Cost Efficient AlN Templates for Deep Ultraviolet Light Devices

2021 ◽  
Vol 21 (9) ◽  
pp. 4881-4885
Author(s):  
Seung-Jae Lee ◽  
Seong-Ran Jeon ◽  
Young Ho Song ◽  
Young-Jun Choi ◽  
Hae-Gon Oh ◽  
...  
Keyword(s):  
Vapor Phase ◽  
Vapor Phase Epitaxy ◽  
Hydride Vapor Phase Epitaxy ◽  
Threading Dislocation ◽  
Sapphire Substrates ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Order Of Magnitude ◽  
Cost Efficient ◽  
Patterned Sapphire Substrates

We report the characteristics of AlN epilayers grown directly on cylindrical-patterned sapphire substrates (CPSS) by hydride vapor-phase epitaxy (HVPE). To evaluate the effect of CPSS, we analyzed the threading dislocation densities (TDDs) of AlN films grown simultaneously on CPSS and flat sapphire substrate (FSS) by transmission electron microscopy (TEM). The corresponding TDD is measured to be 5.69 x 108 cm−2 for the AlN sample grown on the CPSS that is almost an order of magnitude lower than the value of 3.43 × 109 cm−2 on the FSS. The CPSS contributes to reduce the TDs originated from the AlN/sapphire interface via bending the TDs by lateral growth during the coalescence process. In addition, the reduction of direct interface area between AlN and sapphire by CPSS reduce the generation of TDs.

Advanced Si-based Semiconductors for Energy and Photonic Applications

2009 ◽  
Vol 156-158 ◽  
pp. 77-84 ◽  
Author(s):  
J. Kouvetakis ◽  
Jose Menendez ◽  
John Tolle
Keyword(s):  
Precursor Chemistry ◽  
Group Iv ◽  
Device Fabrication ◽  
Interface Microstructure ◽  
Si Substrates ◽  
Group Iv Semiconductors ◽  
Dislocation Densities ◽  
Potential Applications ◽  
Molecular Mixtures ◽  
Lattice Matched

Group-IV semiconductors, including alloys incorporating Sn, have been grown on dimensionally dissimilar Si substrates using novel molecular hydride chemistries with tunable reactivities that enable low temperature, CMOS compatible integration via engineering of the interface microstructure. Here we focus on properties of three such Ge-based systems including: (1) device quality Ge layers with thicknesses >5m possessing dislocation densities <105/cm2 are formed using molecular mixtures of Ge2H6 and highly reactive (GeH3)2CH2 organometallic additives circumventing the classical Stranski-Krastanov growth mechanism, (2) metastable GeSn alloys are grown on Si via reactions of Ge2H6 and SnD4, and (3) ternary SiGeSn analogs are produced lattice-matched to Ge-buffered Si using admixtures of SiGeH6, SiGe2H8, SnD4, Ge2H6, and Si3H8. Optical experiments and prototype device fabrication demonstrate that the ternary SiGeSn system represents the first group-IV alloy with a tunable electronic structure at fixed lattice constant, effectively decoupling band gap and strain and eliminating the most important limitation in device designs based on group-IV materials. Doping at levels higher than 1019 cm-3 (both p and n-type) is achieved for all the above semiconductor systems using a similar precursor chemistry approach. Electrical and infrared optical experiments demonstrate that doped GeSn and SiGeSn have mobilities that compare or exceed that of bulk Ge. The potential applications of these materials, including micro- and optoelectronics as well as photovoltaics and thermoelectricity, are discussed.

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