scholarly journals Experimental and simulation studies of radiation‐induced single event burnout in SiC‐based power MOSFETs

2021 ◽  
Author(s):  
Chao Peng ◽  
Zhifeng Lei ◽  
Ziwen Chen ◽  
Shaozhong Yue ◽  
Zhangang Zhang ◽  
...  
Keyword(s):  
Simulation Studies ◽  
Single Event ◽  
Power Mosfets ◽  
Radiation Induced

Mechanism for single-event burnout of power MOSFETs and its characterization technique

1992 ◽  
Vol 39 (6) ◽  
pp. 1698-1703 ◽  
Author(s):  
S. Kuboyama ◽  
S. Matsuda ◽  
T. Kanno ◽  
T. Ishii
Keyword(s):  
Single Event ◽  
Power Mosfets ◽  
Characterization Technique

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs

2018 ◽  
Vol 88-90 ◽  
pp. 936-940 ◽  
Author(s):  
S. Azimi ◽  
L. Sterpone ◽  
B. Du ◽  
L. Boragno
Keyword(s):  
Single Event ◽  
Single Event Transients ◽  
Radiation Induced

Radiation-Induced Single-Event Effects on the Van Allen Probes Spacecraft

2017 ◽  
Vol 64 (11) ◽  
pp. 2782-2793 ◽  
Author(s):  
Richard H. Maurer ◽  
Kristin Fretz ◽  
Matthew P. Angert ◽  
David L. Bort ◽  
John O. Goldsten ◽  
...  
Keyword(s):  
Single Event ◽  
Single Event Effects ◽  
Van Allen Probes ◽  
Radiation Induced

scholarly journals Study of single event upsets (SEUS) a survey and analysis

2021 ◽  
Author(s):  
Sheldon Mark Foulds
Keyword(s):  
Error Control ◽  
Hamming Code ◽  
Single Event ◽  
Electronic Circuits ◽  
Error Control Coding ◽  
Computing Systems ◽  
Single Event Upsets ◽  
Triple Modular Redundancy ◽  
Radiation Induced ◽  
Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

Impact of Device Structure on Neutron-Induced Single-Event Effect in SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 738-741
Author(s):  
Hiroshi Kono ◽  
Teruyuki Ohashi ◽  
Takao Noda ◽  
Kenya Sano
Keyword(s):  
Threshold Voltage ◽  
Drift Region ◽  
Single Event ◽  
Drain Voltage ◽  
Device Structure ◽  
Pin Diodes ◽  
Power Mosfets ◽  
Single Event Effect ◽  
Significant Difference ◽  
Avalanche Breakdown Voltage

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.

Impact of Varied Buffer Layer Designs on Single-Event Response of 1.2-kV SiC Power MOSFETs

2020 ◽  
Vol 67 (9) ◽  
pp. 3698-3704
Author(s):  
Jiang Lu ◽  
Jiawei Liu ◽  
Xiaoli Tian ◽  
Hong Chen ◽  
Yidan Tang ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Single Event ◽  
Power Mosfets ◽  
Event Response
Sign in / Sign up

Export Citation Format

Share Document