Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

I. Polian; I. Pomeranz; S.M. Reddy; B. Becker

doi:10.1049/ip-cdt:20040141

Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20040141 ◽

2004 ◽

Vol 151 (3) ◽

pp. 235 ◽

Cited By ~ 8

Author(s):

I. Polian ◽

I. Pomeranz ◽

S.M. Reddy ◽

B. Becker

Keyword(s):

Exact Computation ◽

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Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2057459 ◽

2011 ◽

Vol 19 (10) ◽

pp. 1907-1911

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Quality Metric ◽

Transition Fault ◽

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Cyclic stress tests for full scan circuits

Proceedings 13th IEEE VLSI Test Symposium ◽

10.1109/vtest.1995.512622 ◽

1995 ◽

Cited By ~ 5

Author(s):

V. Dabholkar ◽

S. Chakravarty ◽

J. Najm ◽

J. Patel

Keyword(s):

Cyclic Stress ◽

Stress Tests ◽

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Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183159 ◽

2003 ◽

Cited By ~ 4

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Test ◽

Static Test ◽

Test Compaction ◽

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Test Sets ◽

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A test application scheme for embedded full-scan circuits to reduce testing costs

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224407 ◽

2003 ◽

Cited By ~ 2

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Application ◽

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Testing Costs

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Static test compaction for diagnostic test sets of full-scan circuits

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2009.0110 ◽

2010 ◽

Vol 4 (5) ◽

pp. 365-373 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Static Test ◽

Test Compaction ◽

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Test Sets ◽

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Revisiting response compaction in space for full scan circuits with nonexhaustive test sets using concept of sequence characterization

Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412) ◽

10.1109/imtc.2003.1208246 ◽

2004 ◽

Author(s):

S.R. Das ◽

M.H. Assaf ◽

E.M. Petriu ◽

W.B. Jone

Keyword(s):

Sequence Characterization ◽

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Test Sets ◽

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Failure analysis for full-scan circuits

Proceedings of 1995 IEEE International Test Conference (ITC) ◽

10.1109/test.1995.529892 ◽

2002 ◽

Cited By ~ 26

Author(s):

K. De ◽

A. Gunda

Keyword(s):

Failure Analysis ◽

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Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2005.858102 ◽

2005 ◽

Vol 54 (6) ◽

pp. 2310-2328 ◽

Cited By ~ 5

Author(s):

S.R. Das ◽

C.V. Ramamoorthy ◽

M.H. Assaf ◽

E.M. Petriu ◽

W.-B. Jone ◽

...

Keyword(s):

Fault Simulation ◽

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Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

IEEE Transactions on Computers ◽

10.1109/tc.2004.118 ◽

2004 ◽

Vol 53 (12) ◽

pp. 1569-1581 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Lower Bound ◽

Static Test ◽

Test Compaction ◽

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Test Sets ◽

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Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

Journal of Systems Architecture ◽

10.1016/s1383-7621(00)00054-0 ◽

2001 ◽

Vol 47 (3-4) ◽

pp. 357-373

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Design For Testability ◽

Delay Faults ◽

Complete Coverage ◽

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