Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders

2006 ◽  
Vol 153 (3) ◽  
pp. 207 ◽  
Author(s):  
M. Dubois ◽  
Y. Savaria ◽  
D. Haccoun ◽  
N. Belanger
Keyword(s):  
Low Power ◽  
Shift Register ◽  
Convolutional Encoders

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

scholarly journals Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 92 ◽  
Author(s):  
Mohammad Badal ◽  
Mamun Reaz ◽  
Zinah Jalil ◽  
Mohammad Bhuiyan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Shift Register ◽  
Cmos Process ◽  
Flip Flop ◽  
Rfid Tag

scholarly journals A low power 12 bit flux shuttle shift register with Nb technology

1997 ◽  
Vol 7 (2) ◽  
pp. 2983-2986 ◽  
Author(s):  
R. Lochschmied ◽  
R. Herwig ◽  
M. Neuhaus ◽  
W. Jutzi
Keyword(s):  
Low Power ◽  
Shift Register
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