scholarly journals Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 92 ◽  
Author(s):  
Mohammad Badal ◽  
Mamun Reaz ◽  
Zinah Jalil ◽  
Mohammad Bhuiyan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Shift Register ◽  
Cmos Process ◽  
Flip Flop ◽  
Rfid Tag

Low-Power Digital Part Design for a LF RFID tag in a Double-Poly 180 nm CMOS Process

2021 ◽  
Author(s):  
Kirill D. Liubavin ◽  
Igor V. Ermakov ◽  
Alexander Y. Losevskoy ◽  
Andrey V. Nuykin ◽  
Alexander S. Strakhov
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Rfid Tag ◽  
Digital Part

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

Low power D flip-flop serial in/parallel out based shift register

2016 ◽  
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Arvin Mahmoudbeik ◽  
Torikul Islam Badal ◽  
Mamun Bin Ibne Reaz ◽  
Labonnah F. Rahman
Keyword(s):  
Low Power ◽  
Shift Register ◽  
Flip Flop

scholarly journals Low Power and Low Complexity Flip-Flop Design using MIFGMOS

2018 ◽  
Vol 7 (3.1) ◽  
pp. 183
Author(s):  
U Ragavendran ◽  
M Ramachandran
Keyword(s):  
Low Power ◽  
Cochlear Implants ◽  
Low Complexity ◽  
Floating Gate ◽  
Cmos Process ◽  
Process Technology ◽  
Process Data ◽  
Flip Flop ◽  
Passive Devices ◽  
Sequential Logic

Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.  

scholarly journals A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

2018 ◽  
Vol 13 (2) ◽  
pp. 1-6
Author(s):  
Tarcisio Oliveira Moraes Junior ◽  
Raimundo Carlos Silvério Freire ◽  
Cleonilson Protásio de Souza
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Dissipation ◽  
High Efficiency ◽  
Control Circuit ◽  
Experimental Results ◽  
Cmos Process ◽  
Leakage Currents ◽  
Ultra Low Power ◽  
Rectifier Circuits

In MOSFET-transistor based rectifier circuits, leakage currents occur through both source-bulk and drain-bulk connections of their transistors causing some power dissipation decreasing their efficiency. Such a scenario is more worrying in ultra-low power circuits as those used in energy harvesting. As a solution, in this work it is proposed a control circuit of transistor bulk biasing that switches the bulk bias in an efficient way assuring adequate inversion of the source-bulk and drain-bulk junctions. The rectifier based on the proposed bulk biasing control circuit shows to be a high-efficiency one capable of reducing the leakage currents. To obtain experimental results, the circuit was fabricated in a 130 nm CMOS process and tested on a micromanipulator. The results were compared with other works where it is observed that the efficiency of our proposal reaches up to 72.5% or 5% higher that the best previous one.

Design of a Novel Digital Baseband for UHF RFID Tag

2014 ◽  
Vol 513-517 ◽  
pp. 2938-2942
Author(s):  
Wei Lv ◽  
Xin An Wang ◽  
Ji Ting Su
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Peak Power ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Power Module ◽  
Chip Area ◽  
Rfid Tag ◽  
Digital Baseband

This paper presents a novel low-power digital baseband for UHF RFID tag. The design is complied with a modified ISO 18000-6C protocol. In order to reduce the peak power, module-reuse and other advanced low power techniques are applied. And a novel baseband architecture is discussed, which fulfills the protocol functions and reduces power consumption. The whole tag chip, including digital baseband, RF/analog frontend and memory, has been taped out using TSMC 0.18um CMOS process. The chip area is 89234 um2 excluding test pads. Its power consumption is 11.63uw under 1.1v power supply.

scholarly journals Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 676
Author(s):  
Labonnah Farzana Rahman ◽  
Mohammad Marufuzzaman ◽  
Lubna Alam ◽  
Mazlin Bin Mokhtar
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Output Voltage ◽  
High Efficiency ◽  
Charge Pump ◽  
Design Methods ◽  
Optimization Techniques ◽  
Cmos Process ◽  
Advantages And Disadvantages ◽  
Continuous Power

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

A 20-mV Input DC/DC Converter for Energy Harvesting Applications

2015 ◽  
Vol 24 (05) ◽  
pp. 1550070 ◽  
Author(s):  
Zheng Yang ◽  
Jingmin Wang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Management ◽  
High Efficiency ◽  
Low Power Design ◽  
Input Voltage ◽  
Voltage Source ◽  
Storage Capacitor ◽  
Cmos Process ◽  
Low Input

A low input step-up DC/DC converter and power manager in 0.18-μm CMOS process is presented. The proposed converter can work with the input voltage as low as 20 mV. The extremely low input voltage makes it suitable for energy harvesting and power management. Four logic controlled outputs provide the best voltage for various applications to accommodate low power design requirements. A low current low dropout regulator (LDO) is utilized to provide a regulated 2.2 V output for powering low power processors or other low power integrated circuit (ICs). Reserve energy on the storage capacitor CSTORE provides power when the input voltage source is unavailable, thus prolongs the life of the system and expands the application range. Extremely low quiescent current (6 μA) and high efficiency design (64%@300 μA load current) ensure the fastest possible charge times of the output reservoir capacitor. This work provides a complete power management solution for wireless sensing and data acquisition.

scholarly journals A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 589 ◽  
Author(s):  
Tianchen Shen ◽  
Jiabing Liu ◽  
Chunyi Song ◽  
Zhiwei Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Flip Flop ◽  
Mode Control ◽  
Power Operation

A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.

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