In recent days, On-Chip Communication is a major requirement in modern systems that produce efficient communication with less complexity and high throughput. Due to heavy traffic and increasing Network-On Chip (NoC) size, the routing algorithm produces poor performances. Normally, round-robin and matrix arbiters are used in NoC for high-speed switches. In this research work, three different types of arbiter algorithms are used such as priority algorithm, Time Division Multiplexed (TDM) algorithm, and Viterbi algorithm to improve the linearity of the NOC. Initially, the priority algorithm helps to minimize traffic congestion when the arbiter is in a busy mode. Second, the fairness and Quality of Service (QoS) of the NoC structure are analyzed by the TDM algorithm. Finally, the Viterbi algorithm based error prediction process is done in an NoC structure. Due to the usage of three proposed arbiter algorithms, the area of NoC can be reduced. The packet can be reached to the destination by using the arbitration process with less loss. In this research, the proposed methodology is called as Low AreaFault-Tolerant Adaptive Arbitration based NoC architecture (LAFTAA- NoC architecture). Finally, the Field Programmable Gate Array (FPGA) performance is evaluated such as LUT, flip flop, slices, and frequency in Spartan 6 hardware. In the proposed method, 2.42% of LUT, 3.1% of flip flop, and 8.63% of slices have reduced when compared to existing work.
Central Routing Algorithm: An Alternative Solution to Avoid Mesh Topology in iBGP