scholarly journals An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection

2016 ◽  
Vol 3 (1) ◽  
pp. 77-84 ◽  
Author(s):  
Sanjeev Kumar Jain ◽  
Basabi Bhaumik
Keyword(s):  
Cardiovascular Disease ◽  
Integrated Circuit ◽  
Energy Efficient ◽  
Feature Detection ◽  
Disease Detection ◽  
Application Specific Integrated Circuit ◽  
Application Specific

scholarly journals Simultaneous Voltage and Current Measurement Instrumentation Amplifier for ECG and PPG Monitoring

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim
Keyword(s):  
Integrated Circuit ◽  
Cardiovascular Health ◽  
Current Noise ◽  
Instrumentation Amplifier ◽  
Current Sensing ◽  
Application Specific Integrated Circuit ◽  
Time Division ◽  
Electrocardiogram Ecg ◽  
First Time ◽  
Application Specific

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.

CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS

1994 ◽  
Vol 04 (04) ◽  
pp. 501-516 ◽  
Author(s):  
BOGDAN T. FIJALKOWSKI ◽  
JAN W. KROSNICKI
Keyword(s):  
Direct Current ◽  
Integrated Circuit ◽  
Environmentally Friendly ◽  
Alternating Current ◽  
Switching Frequency ◽  
Neuro Fuzzy ◽  
Interior Permanent Magnet ◽  
Application Specific Integrated Circuit ◽  
Computer Processor ◽  
Application Specific

Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.

scholarly journals Design of ASIC Square Calculator Using AncientVedic Mathematics

2018 ◽  
Vol 7 (2.23) ◽  
pp. 464
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Shubhajit Pal
Keyword(s):  
Integrated Circuit ◽  
Software Tool ◽  
Logic Gates ◽  
Digital Logic ◽  
Simple Design ◽  
Innovative Design ◽  
Circuit Asic ◽  
Vedic Mathematics ◽  
Application Specific Integrated Circuit ◽  
Application Specific

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.  

scholarly journals A P4-Enabled RINA Interior Router for Software-Defined Data Centers

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Data Transfer ◽  
Great Promise ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Networking Technologies ◽  
Application Specific

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

scholarly journals Miniaturized Optical Encoder with Micro Structured Encoder Disc

2019 ◽  
Vol 9 (3) ◽  
pp. 452 ◽  
Author(s):  
Jonathan Seybold ◽  
André Bülau ◽  
Karl-Peter Fritz ◽  
Alexander Frank ◽  
Cor Scherjon ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Precision Machining ◽  
Signal Acquisition ◽  
Optical Encoder ◽  
Diffraction Of Light ◽  
Application Specific Integrated Circuit ◽  
Ultra Precision ◽  
Absolute Encoder ◽  
Micro Structures ◽  
Application Specific

A novel optical incremental and absolute encoder based on an optical application-specific integrated circuit (opto-ASIC) and an encoder disc carrying micro manufactured structures is presented. The physical basis of the encoder is the diffraction of light using a reflective phase grating. The opto-ASIC contains a ring of photodiodes that represents the encryption of the encoder. It also includes the analog signal conditioning, the signal acquisition, and the control of a light source, as well as the digital position processing. The development and fabrication of the opto-ASIC is also described in this work. A laser diode was assembled in the center on top of the opto-ASIC, together with a micro manufactured polymer lens. The latter was fabricated using ultra-precision machining. The encoder disc was fabricated using micro injection molding and contains micro structures forming a blazed grating. This way, a 10-bit optical encoder with a form factor of only 1 cm3 was realized and tested successfully.

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