Flicker noise cancellation technique for low-voltage direct-conversion mixers

2007 ◽  
Vol 43 (19) ◽  
pp. 1020 ◽  
Author(s):  
S. Asgaran ◽  
M. Jamal Deen
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Direct Conversion ◽  
Noise Cancellation

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Analytical Formula ◽  
Direct Conversion ◽  
Low Noise ◽  
Cmos Process ◽  
Passive Mixer ◽  
Dc Offset ◽  
Front End ◽  
Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers

2001 ◽  
Vol 36 (1) ◽  
pp. 102-109 ◽  
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Noise Rejection

Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers"

2002 ◽  
Vol 37 (8) ◽  
pp. 1090
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Noise Rejection
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