An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers

2001 ◽  
Vol 36 (1) ◽  
pp. 102-109 ◽  
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Noise Rejection

Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers"

2002 ◽  
Vol 37 (8) ◽  
pp. 1090
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Noise Rejection

Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers"

2002 ◽  
Vol 37 (8) ◽  
pp. 1090-1090
Author(s):  
T. Melly ◽  
A. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Noise Rejection

scholarly journals Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1936
Author(s):  
Luis Miguel Carvalho Freitas ◽  
Fernando Morgado-Dias
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Flicker Noise ◽  
Image Sensor ◽  
Low Noise ◽  
Image Noise ◽  
Frame Rate ◽  
Direct Role ◽  
Sigma Delta

Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

scholarly journals Low-power 3V single supply lock-in amplifier

1970 ◽  
pp. 2
Author(s):  
J. Aguirre ◽  
N. Medrano ◽  
B. Calvo ◽  
S. Celma
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flicker Noise ◽  
Average Power ◽  
Wireless Sensor ◽  
Reference Frequency ◽  
Sinusoidal Oscillator ◽  
Average Power Consumption ◽  
Sinusoidal Input ◽  
Lock In

In extreme high noise level environments, linear filtering is not a suitable processing method and special techniques for accurately extracting sensor signal information should be considered. An interesting possibility are lock-in amplifiers (LIA), which use the phase sensitive detection technique (PSD) to take out the data signal at a specific reference frequency fo while noise signals at frequencies other than fo are rejected and do not affect significantly the measurement. Current commercial LIAs are expensive, heavy and power consuming devices, which preclude their use in portable sensing systems. Thus, this work analyses the possibility of exporting this technique to low-power low-voltage (LPLV) embedded applications. In particular, the aim is to implement a signal conditioning lock-in architecture suitable for 3V single battery-operated wireless sensor nodes. This implies to re-design all the processing elements in single supply -most reported LIAs are designed using dual power supply- and compatible with the power requirements of a wireless sensor network node. Further, looking for a compact LPLV solution, instead of a traditional sinusoidal input, a square wave input is considered, which can be directly obtained from the embedded microcontroller, thus avoiding blocks like a sinusoidal oscillator or function generator. Figure 1 shows the proposed block diagram and a photograph of the implemented device. Experimental results for signals buried in white noise, flicker noise, interference contamination and common-mode voltage contamination confirm the capability of the proposed solution to recover information from signal to noise ratios down to 24 dB with errors below 6% with an average power consumption of only 5 mW in full operation, being able to process signals with frequencies up to 43 kHz, as shown in Figure 2.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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