scholarly journals Low Power Digital Multimedia Telecommunication Designs

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 301-315 ◽  
Author(s):  
Koon-Shik Cho ◽  
Jun-Dong Cho
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Communication Systems ◽  
Matched Filter ◽  
Optimization Technique ◽  
Low Power Design ◽  
Multimedia Systems ◽  
Wireless Multimedia ◽  
Design Constraint ◽  
Power Capability

The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications. This paper presents possible optimization technique to reduce the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the sample storage in parallel correlator, using complex matched filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the distortion values become great than the minimum distortion value in motion estimation, and exploiting the relative occurrence of zero-valued DCT coefficient in IDCT.

Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip

2016 ◽  
pp. 323-351
Author(s):  
Bhagwan Das ◽  
Mohammad Faiz Liew Abdullah
Keyword(s):  
Low Power ◽  
Communication System ◽  
Communication Systems ◽  
High Speed ◽  
Vlsi Design ◽  
Low Power Design ◽  
Vlsi Chip ◽  
Vlsi System ◽  
Large Scale Integration ◽  
28 Nm

The low power design of Very Large Scale Integration (VLSI) system is one of the hot topic in research. In this chapter, the low power design for VLSI based high-speed communication is realized over 28 nm VLSI chip packed in UltraScale Field Programming Gate Array (FPGA) using proposed technique. The high-speed communication system is taken as case study for the low power design of VLSI system. Similarly, various VLSI design system can be realized to achieve the low power VLSI system design goal. High-speed communication systems provide the smooth operation for global internet traffic and requires high power devices and components.IO standard is powerful interface tool that provides low power consumption using the fast signal termination by mean of electrical characteristics. In result for this work, more than 96% power reduction is achieved for VLSI based high-speed communication system, when operated at 500 GHZ, 900 GHz, 10 THz and 17 THz carrier frequencies using the High-Speed Unterminated Logic IO Standard. The power analysis is performed using XPA analyzer in Xilinx suite.

Low-Power Design Solutions for Wireless Multimedia SoCs

2009 ◽  
Vol 26 (2) ◽  
pp. 20-29 ◽  
Author(s):  
Jean-Pierre Schoellkopf ◽  
Philippe Magarshack
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Wireless Multimedia ◽  
Design Solutions

Power mad [low-power design]

2004 ◽  
Vol 18 (3) ◽  
pp. 37
Author(s):  
J. Frenkil
Keyword(s):  
Low Power ◽  
Low Power Design

Low-Power Motion Estimation Processor with 3D Stacked Memory

2015 ◽  
Vol E98.A (7) ◽  
pp. 1431-1441 ◽  
Author(s):  
Shuping ZHANG ◽  
Jinjia ZHOU ◽  
Dajiang ZHOU ◽  
Shinji KIMURA ◽  
Satoshi GOTO
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Stacked Memory

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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