Combined Max-Log-MAP and Log-MAP of turbo codes

2004 ◽  
Vol 40 (4) ◽  
pp. 251 ◽  
Author(s):  
S.-J. Park
Keyword(s):  
Turbo Codes ◽  
Log Map

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

Constant log-MAP decoding algorithm for duo-binary turbo codes

2006 ◽  
Vol 42 (12) ◽  
pp. 709 ◽  
Author(s):  
S. Papaharalabos ◽  
P. Sweeney ◽  
B.G. Evans
Keyword(s):  
Turbo Codes ◽  
Decoding Algorithm ◽  
Map Decoding ◽  
Log Map

scholarly journals Efficient and low latency turbo encoder design using Verilog-Hdl

2017 ◽  
Vol 7 (1.5) ◽  
pp. 37 ◽  
Author(s):  
M Siva Kumar ◽  
S Syed Shameem ◽  
M.N.V. Raghu Sai ◽  
Dheeraj Nikhil ◽  
P. Kartheek ◽  
...  
Keyword(s):  
Turbo Codes ◽  
Iterative Decoding ◽  
Low Complexity ◽  
Control Performance ◽  
Hardware Complexity ◽  
Verilog Hdl ◽  
Parallel Connection ◽  
Exponential Expansion ◽  
Turbo Encoder ◽  
Log Map

Low complexity turbo-like codes based totally on the simple trellis or simple graph shape consequences in encoding with low complexity. Out of this Convolution, encoder and turbo codes are widely used due to the splendid errors control performance. The most famous communications encoding set of rules, the iterative deciphering calls for an exponential expansion in hardware complexity to acquire expanded encode accuracy. This paper makes a usage of Log-Map based Iterative decoding technique and specialty in the conclusion of the turbo encoder. The rapid codes are designed with the help of Recursive Systematic Convolution and are separated thru interleave, which (thing used to rearrange the bit collection) plays an essential position within the encoding technique. This paper offers the design of the parallel connection of Recursive Systematic Convolution (RSC) encoders and interleave to restrict postpone, results to form a turbo Encoder. The turbo Encoder is designed by way of Verilog-HDL and Synthesized through Xilinx ISE

An Improved Log-MAP Algorithm For BICM-ID Embedded Turbo Codes

2013 ◽  
Vol 433-435 ◽  
pp. 634-638
Author(s):  
Jian Wang ◽  
Jian Ping Li
Keyword(s):  
Turbo Codes ◽  
Iterative Decoding ◽  
Optimal Algorithm ◽  
Linear Interpolation ◽  
Coded Modulation ◽  
Logarithmic Correction ◽  
Map Algorithm ◽  
Lower Complexity ◽  
Performance Gains ◽  
Log Map

This paper presents a novel decoding algorithm for bit-interleaved coded modulation iterative decoding (BICM-ID) embedded turbo codes. It can yield good bit error rate (BER) performance with much lower complexity. The improved algorithm exploits a linear interpolation and optimal mean square approximation function to replace the logarithmic correction in the Jacobian logarithmic function based on the MacLaurin Series, which avoids complicated logarithm look-up table operations in Log-MAP. Simulation results show that the novel algorithm obtains can offer almost equivalent performance to the optimal algorithm. Compared with the improved MAX-Log-MAP algorithm, the proposed algorithm can reduce about 34% of computational complexity, meanwhile it achieves 0.1db-0.16db performance gains.

Low Power Design of near Shannon Limit Coding: Turbo Codes

2012 ◽  
Vol 433-440 ◽  
pp. 7213-7217
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity
Keyword(s):  
Low Power ◽  
Turbo Codes ◽  
Channel Coding ◽  
Low Power Design ◽  
Maximum A Posteriori ◽  
A Posteriori ◽  
Turbo Decoder ◽  
Coding Schemes ◽  
Decoder Design ◽  
Log Map

In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.

Research and Realization by FPGA of Turbo Codes

2012 ◽  
Vol 588-589 ◽  
pp. 765-768
Author(s):  
Jin Xu ◽  
Ying Zhao ◽  
Shu Qiang Duan
Keyword(s):  
Turbo Codes ◽  
Channel Coding ◽  
Turbo Code ◽  
Noise Signal ◽  
Low Noise ◽  
Random Coding ◽  
Map Algorithm ◽  
Key Issues ◽  
Turbo Encoder ◽  
Log Map

Turbo Code is a channel coding with excellent error-correcting performance in the condition of low noise-signal ratio.It has a superior decoding performance approaching the Shannon limit by adopting the random coding and decoding. This paper focuses on Turbo code and its implementation with FPGA and deeply analyzes the decoding theory and algorithm of Turbo code. Firstly, it analyzes the decoding theory of Turbo code. Then, it discusses key issues in the process of implementation with the most excellent and complicated Max—log—MAP algorithm. At last, it ends up with the Turbo encoder and decoding algorithm which hardware is successfully implemented finally.

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