Rail-to-rail amplifier input stage with constant gm and commonmode elimination

2002 ◽  
Vol 38 (24) ◽  
pp. 1491 ◽  
Author(s):  
T.W. Fischer ◽  
A.I. Karsilayan
Keyword(s):  
Input Stage ◽  
Amplifier Input ◽  
Rail To Rail

0.9 V rail-to-rail constant gm CMOS amplifier input stage

2009 ◽  
Vol 45 (23) ◽  
pp. 1145 ◽  
Author(s):  
C.-W. Lu ◽  
C.-M. Hsiao
Keyword(s):  
Input Stage ◽  
Amplifier Input ◽  
Rail To Rail ◽  
Cmos Amplifier

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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