Constant transconductance CMOS amplifier input stage with rail-to-rail input common mode voltage range

1995 ◽  
Vol 42 (5) ◽  
pp. 366-368 ◽  
Author(s):  
K. Nagaraj
Keyword(s):  
Common Mode ◽  
Voltage Range ◽  
Input Stage ◽  
Amplifier Input ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
Constant Transconductance ◽  
Cmos Amplifier

scholarly journals A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

2021 ◽  
Vol 11 (6) ◽  
pp. 2528 ◽  
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Common Mode ◽  
Input Stage ◽  
Fully Differential ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
Ultralow Power

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

0.9 V rail-to-rail constant gm CMOS amplifier input stage

2009 ◽  
Vol 45 (23) ◽  
pp. 1145 ◽  
Author(s):  
C.-W. Lu ◽  
C.-M. Hsiao
Keyword(s):  
Input Stage ◽  
Amplifier Input ◽  
Rail To Rail ◽  
Cmos Amplifier

On the input common-mode voltage range of CMOS bulk-driven input stages

2010 ◽  
Vol 39 (6) ◽  
pp. 649-664 ◽  
Author(s):  
Juan M. Carrillo ◽  
Guido Torelli ◽  
Miguel A. Domínguez ◽  
J. Francisco Duque-Carrillo
Keyword(s):  
Common Mode ◽  
Voltage Range ◽  
Common Mode Voltage

A Radiation-Hardened and ESD-Optimized Wireline Driver With Wide Terminal Common-Mode Voltage Range

2018 ◽  
Vol 65 (1) ◽  
pp. 566-572
Author(s):  
Xun Xiang ◽  
Xingguo Gao ◽  
Fan Liu ◽  
Mingdong Li ◽  
Shalin Huang ◽  
...  
Keyword(s):  
Common Mode ◽  
Voltage Range ◽  
Common Mode Voltage ◽  
Radiation Hardened

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

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