InAlAs avalanche photodiodes with very thin multiplication layer of 0.1 [micro sign]m for high-speed and low-voltage-operation optical receiver

2000 ◽  
Vol 36 (21) ◽  
pp. 1807 ◽  
Author(s):  
T. Nakata ◽  
I. Watanabe ◽  
K. Makita ◽  
T. Torikai
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Avalanche Photodiodes ◽  
Optical Receiver ◽  
Low Voltage Operation

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

2010 ◽  
Vol 19 (06) ◽  
pp. 1275-1297
Author(s):  
WEN-TZENG HUANG ◽  
SUN-YEN TAN ◽  
YUAN-JEN CHANG
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Low Voltage ◽  
Switching Noise ◽  
Decoupling Capacitors ◽  
Input Noise ◽  
Low Voltage Operation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching ◽  
Ibis Model

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

Overview and Technical Trend of Chain FeRAM

2010 ◽  
Vol 1250 ◽  
Author(s):  
Daisaburo Takashima
Keyword(s):  
Marketing Strategy ◽  
High Speed ◽  
Low Voltage ◽  
Disk Drive ◽  
Memory Systems ◽  
Ferroelectric Capacitor ◽  
Performance Improvements ◽  
Cell Signal ◽  
Low Voltage Operation ◽  
High Bandwidth

AbstractA chain FeRAMTM is the best solution to realize high-speed and high-bandwidth nonvolatile RAM with low power dissipation. In this paper, the overview of chain FeRAM, the technical trend for FeRAM scaling and the marketing strategy are presented. First of all, the concept and performance of chain FeRAM are described. Secondly, the status and history of chain FeRAM development are presented. Thirdly, four kinds of scaling strategies for chain FeRAM are presented; (1) A shrink trend of chain cell including a capacitor plug shared with twin cells, and process techniques including Ir/TiAlN-barrier metal and MOCVD-PZT with SrRuO3 electrode, which are installed in 16Kb, 8Mb, 32Mb, 64Mb and 128Mb chain FeRAMs, (2) Capacitor damage suppression processes to reinforce step coverage and protect H2 damage even in 0.1μm2 capacitor of 128Mb, (3) A scalable array architecture such as an octal / quad bitline architecture to reduce bitline capacitance and ensure enough cell signal in scaled ferroelectric capacitor, and (4) A ferroelectric capacitor overdrive technique by driving shield-bitlines to enlarge tail-to-tail cell signal in low voltage operation of 1.3V. Fourthly, future direction of chain FeRAM is discussed. The vertical capacitor is one of candidates for gigabit-scale chain FeRAMs, and solves signal problem and achieves small 4F2 cell without contact formation. Finally, the marketing strategy to take full advantage of chain FeRAM is presented. A nonvolatile FeRAM cache is the promising candidate to achieve high bandwidth memory systems. Applications of chain FeRAM to solid-state drive (SSD) and hard-disk drive (HDD) and their system performance improvements are demonstrated.

scholarly journals A Fast ALU Design in CMOS for Low Voltage Operation

VLSI Design ◽  
2002 ◽  
Vol 14 (4) ◽  
pp. 315-327 ◽  
Author(s):  
A. Srivastava ◽  
D. Govindarajan
Keyword(s):  
Delay Time ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Substrate Bias ◽  
Back Gate ◽  
Low Voltage Operation ◽  
Logical Operations ◽  
Ripple Carry Adder ◽  
Speed Advantage

A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in 1.2 μm N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to |0.4| V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design.

High speed silicon photonic crystal waveguide modulator for low voltage operation

2007 ◽  
Vol 90 (7) ◽  
pp. 071105 ◽  
Author(s):  
Lanlan Gu ◽  
Wei Jiang ◽  
Xiaonan Chen ◽  
Li Wang ◽  
Ray T. Chen
Keyword(s):  
Photonic Crystal ◽  
High Speed ◽  
Low Voltage ◽  
Photonic Crystal Waveguide ◽  
Low Voltage Operation ◽  
Silicon Photonic ◽  
Waveguide Modulator

High Speed and Low Voltage Operation of CMOS Inverters Using SOI-MOSFET with Body Terminal

1997 ◽  
Author(s):  
T. Matsumoto ◽  
N. Terao ◽  
S. Pidin ◽  
H. Kurino ◽  
M. Koyanagi
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Soi Mosfet ◽  
Low Voltage Operation
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