Sign extension bit minimisation algorithm for multi-bit coded multiplier structures for DSP applications

1996 ◽  
Vol 32 (16) ◽  
pp. 1454
Author(s):  
D.V. Poornaiah
Keyword(s):  
Sign Extension ◽  
Dsp Applications

HyDRA: Hybrid Dynamically Reconfigurable Architecture for DSP Applications

2016 ◽  
Vol E99.C (7) ◽  
pp. 866-877 ◽  
Author(s):  
Abdulfattah M. OBEID ◽  
Syed Manzoor QASIM ◽  
Mohammed S. BENSALEH ◽  
Abdullah A. ALJUFFRI
Keyword(s):  
Reconfigurable Architecture ◽  
Dynamically Reconfigurable ◽  
Dsp Applications ◽  
Dynamically Reconfigurable Architecture

A new FPGA architecture suitable for DSP applications

2011 ◽  
Vol 32 (5) ◽  
pp. 055012
Author(s):  
Liyun Wang ◽  
Jinmei Lai ◽  
Jiarong Tong ◽  
Pushan Tang ◽  
Xing Chen ◽  
...  
Keyword(s):  
Fpga Architecture ◽  
Dsp Applications

scholarly journals Smart analytical signature verification for DSP applications

2013 ◽  
Author(s):  
Rozita Teymourzadeh ◽  
Waidhuba Martin Kizito ◽  
Kok Wai Chan ◽  
Mok Vee Hoong
Keyword(s):  
Signature Verification ◽  
Dsp Applications

A flexible module library for custom DSP applications in a multiprocessor environment

1990 ◽  
Vol 25 (3) ◽  
pp. 720-729 ◽  
Author(s):  
E. Blokken ◽  
H. De Keulenaer ◽  
F. Catthoor ◽  
H.J. De Man
Keyword(s):  
Dsp Applications

scholarly journals Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-20
Author(s):  
Gongyu Wang ◽  
Greg Stitt ◽  
Herman Lam ◽  
Alan George
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Core Level ◽  
Prediction Methods ◽  
Clock Frequency ◽  
Worst Case ◽  
Model Based ◽  
Dsp Applications

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

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