2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769513093

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An efficient algorithm for pointer-to-array access conversion for compiling and optimizing DSP applications

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955200 ◽

2001 ◽

Cited By ~ 5

Author(s):

van Engelen ◽

Gallivan

Keyword(s):

Efficient Algorithm ◽

Dsp Applications

Download Full-text

Wrapped system call in communication and execution fusion OS: CEFOS

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955199 ◽

2001 ◽

Author(s):

Nakayama ◽

Tanabayashi ◽

Amamiya

Keyword(s):

System Call

Download Full-text

Cache-In-Memory

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955191 ◽

2001 ◽

Cited By ~ 4

Author(s):

Zawodny ◽

Kogge

Download Full-text

Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955197 ◽

2001 ◽

Cited By ~ 2

Author(s):

Nakajo ◽

Ishii ◽

Yamamoto ◽

Kudo ◽

Yokoyama ◽

...

Keyword(s):

Cache Coherence ◽

Performance Estimation ◽

Proxy Cache ◽

Cache Coherence Protocol

Download Full-text

Characteristics of loop unrolling effect: software pipelining and memory latency hiding

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955198 ◽

2001 ◽

Cited By ~ 3

Author(s):

Hiroyuki ◽

Teruhiko

Keyword(s):

Software Pipelining ◽

Memory Latency ◽

Loop Unrolling

Download Full-text

Power efficient instruction cache for wide-issue processors

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955192 ◽

2001 ◽

Cited By ~ 2

Author(s):

Badulescu ◽

Veidenbaum

Keyword(s):

Power Efficient ◽

Instruction Cache ◽

Wide Issue

Download Full-text

Power reduction in superscalar datapaths through dynamic bit-slice activation

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955193 ◽

2001 ◽

Cited By ~ 2

Author(s):

Ponomarev ◽

Kucuk ◽

Ghose

Keyword(s):

Power Reduction

Download Full-text

An approach towards an analytical characterization of locality and its portability

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955195 ◽

2001 ◽

Cited By ~ 3

Author(s):

Bilardi ◽

Peserico

Keyword(s):

Analytical Characterization

Download Full-text

Innovative Architecture for Future Generation High-Performance Processors and Systems

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955190 ◽

2001 ◽

Keyword(s):

High Performance ◽

Future Generation

Download Full-text

Pipelined memory hierarchies: scalable organizations and application performance

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2001.955196 ◽

2001 ◽

Cited By ~ 1

Author(s):

Bilardi ◽

Ekanadham ◽

Pattnaik

Keyword(s):

Memory Hierarchies ◽

Application Performance

Download Full-text

2001 Innovative Architecture for Future Generation High-Performance Processors and SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An efficient algorithm for pointer-to-array access conversion for compiling and optimizing DSP applications

Wrapped system call in communication and execution fusion OS: CEFOS

Cache-In-Memory

Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation

Characteristics of loop unrolling effect: software pipelining and memory latency hiding

Power efficient instruction cache for wide-issue processors

Power reduction in superscalar datapaths through dynamic bit-slice activation

An approach towards an analytical characterization of locality and its portability

Innovative Architecture for Future Generation High-Performance Processors and Systems

Pipelined memory hierarchies: scalable organizations and application performance

2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications