Low-voltage, low-power, wide-range controllable current amplifier for hearing aids

1994 ◽  
Vol 30 (3) ◽  
pp. 178-180 ◽  
Author(s):  
R. Otte ◽  
A.H.M. van Roermund
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Low Voltage ◽  
Current Amplifier ◽  
Wide Range

Low-voltage low-power controlled attenuator for hearing aids

1993 ◽  
Vol 29 (15) ◽  
pp. 1355 ◽  
Author(s):  
A. van Staveren ◽  
A.H.M. van Roermund
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Low Voltage

scholarly journals An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids

1998 ◽  
Vol 33 (2) ◽  
pp. 291-294 ◽  
Author(s):  
L.P.L. van Dijk ◽  
A.C. van der Woerd ◽  
J. Mulder ◽  
A.H.M. van Roermund
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Delay Line ◽  
Low Voltage ◽  
Ultra Low Power

scholarly journals Energy Efficient Full Swing GDI based Adder Architecture for Arithmetic Applications

2021 ◽  
Author(s):  
Pratibha Aggarwal ◽  
Bharat Garg
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Low Voltage ◽  
Critical Path ◽  
Full Adder ◽  
High Signal ◽  
Cmos Process ◽  
Process Technology ◽  
Wide Range ◽  
Voltage Swing

Abstract Adders are one of the most important digital components used in any arithmetic applications. Many improvements in past have been made to improve its architecture. In this paper, we present two new symmetric designs for Energy efficient full adder cells featuring GDI (Gate-Diffusion Input) logic. The main design objectives for these adder modules are to operate at Low-Power with reduced area but also provide full-voltage swing. In the first (AEG-FA) design, a new approach of Inverted and Non-Inverted Carry-ins were taken to give complementary Carry-out and Sum with desired performance. These were then applied in different combinations to form higher bit width Adder architecture. This provides a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second (PEG-FA) design is based on conventional approach which tries to reduce the critical path delay and lower switching activity in GDI circuit, providing Low-Power and high speed digital component at full voltage swing circuit. Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltage with high signal integrity and driving capability. In order to evaluate the performance of proposed full adders, we incorporated 8-bit ripple carry adders. The studied circuits are optimized for energy efficiency using 45 nm CMOS process technology. The comparison between these novel circuits with standard full adder cells shows improvement in terms of Area, Delay, Power and Power-Delay-Product (PDP), Area-Delay Product (ADP), Area-Power Product (APP). At architecture level proposed adder shows 12.8% over CMOS, 14.8% over hybrid and 11.4% over other GDI logic power savings, by having almost 55% reduction in area.

scholarly journals Low-power ASIC suitable for miniaturized wireless EMG systems

2019 ◽  
Vol 70 (5) ◽  
pp. 393-399 ◽  
Author(s):  
Vilem Kledrowetz ◽  
Roman Prokop ◽  
Lukas Fujcik ◽  
Michal Pavlik ◽  
Jiří Háze
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Voltage ◽  
Cmos Technology ◽  
Instrumentation Amplifier ◽  
Pass Filter ◽  
Delta Sigma ◽  
Pulse Density ◽  
Wide Range

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

Low-voltage low-power infra-red receiver for hearing aids

1992 ◽  
Vol 28 (4) ◽  
pp. 396 ◽  
Author(s):  
A.C. van der Woerd
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Low Voltage ◽  
Infra Red
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