High-temperature leakage current suppression in CMOS integrated circuits

1989 ◽  
Vol 25 (17) ◽  
pp. 1133 ◽  
Author(s):  
S.E. Nordquist ◽  
J.W. Haslett ◽  
F.N. Trofimenkoff
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Leakage Current ◽  
Cmos Integrated Circuits

High Temperature Silicon Carbide CMOS Integrated Circuits

2011 ◽  
Vol 679-680 ◽  
pp. 726-729 ◽  
Author(s):  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
Robin. F. Thompson ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Band Gap ◽  
High Temperatures ◽  
Wide Band ◽  
Cmos Technology ◽  
Cmos Integrated Circuits ◽  
Wide Band Gap ◽  
Circuit Performance

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics

2017 ◽  
Vol 897 ◽  
pp. 669-672 ◽  
Author(s):  
Shinichiro Kuroki ◽  
Tatsuya Kurose ◽  
Hirofumi Nagatsuma ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Leakage Current ◽  
High Voltage ◽  
Logic Gate ◽  
Harsh Environment ◽  
Test Elements ◽  
Voltage Swing

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

An Alternative to High-Temperature and Acid/Solvent-Based Methods for Removing Integrated Circuits from Ceramic or Other Problem Substrates

2005 ◽  
Author(s):  
Carl M. Nail
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Success Rate ◽  
Mechanical Damage ◽  
Test Equipment ◽  
High Success Rate ◽  
Automated Test Equipment ◽  
Removal Method ◽  
Automated Test ◽  
Conventional Methods

Abstract Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.

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