Parity generator circuit using a multistate resonant tunnelling bipolar transistor

1988 ◽  
Vol 24 (24) ◽  
pp. 1506 ◽  
Author(s):  
S. Sen ◽  
F. Capasso ◽  
A.Y. Cho ◽  
D.L. Sivco
Keyword(s):  
Bipolar Transistor ◽  
Resonant Tunnelling ◽  
Generator Circuit ◽  
Parity Generator

Room-temperature resonant tunnelling bipolar transistor XNOR and XOR integrated circuits

1993 ◽  
Vol 29 (20) ◽  
pp. 1802 ◽  
Author(s):  
A.C. Seabaugh ◽  
A.H. Taddiken ◽  
E.A. Beam ◽  
J.N. Randall ◽  
Y.-C Kao ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Room Temperature ◽  
Bipolar Transistor ◽  
Resonant Tunnelling

scholarly journals An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Electrostatic Interactions ◽  
Cmos Technology ◽  
Power Parity ◽  
Ultra Low Power ◽  
Generator Circuit ◽  
Comparison Results ◽  
Low Power Dissipation ◽  
Parity Generator

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

scholarly journals Design of Digital Parity Generator Layout Using 0.7 micron Technology

2018 ◽  
Vol 8 (5) ◽  
pp. 3550
Author(s):  
Wahab Musa ◽  
Sri Wahyuni Dali ◽  
Ade Irawaty Tolago
Keyword(s):  
Integrated Circuit ◽  
Design Method ◽  
Process Technology ◽  
Design Rules ◽  
Test Function ◽  
Data Errors ◽  
Generator Circuit ◽  
Parity Generator ◽  
Simulation Results ◽  
Schematic Circuit

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.<br /><br />

Eleven-bit parity generator with a single, vertically integrated resonant tunnelling device

1988 ◽  
Vol 24 (11) ◽  
pp. 681-683 ◽  
Author(s):  
A.A. Lakhani ◽  
R.C. Potter ◽  
H.S. Hier
Keyword(s):  
Resonant Tunnelling ◽  
Parity Generator

Resonant Tunnelling Bipolar Transistor (RTBT): New Functional Device for Electronics of the Future

1992 ◽  
Vol 38 (2-3) ◽  
pp. 120-132 ◽  
Author(s):  
Susanta Sen ◽  
Federico Capasso ◽  
Fabio Beltram ◽  
Arvind S Vengurlekar
Keyword(s):  
Bipolar Transistor ◽  
Resonant Tunnelling ◽  
The Future
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