Planar normally-off GaAs JFET for high speed logic circuits

1981 ◽  
Vol 17 (25-26) ◽  
pp. 951 ◽  
Author(s):  
Y. Kato ◽  
M. Dohsen ◽  
J. Kasahara ◽  
K. Taira ◽  
N. Watanabe
Keyword(s):  
High Speed ◽  
Logic Circuits

Planar GaAs normally-off j.f.e.t. for high speed logic circuits

1980 ◽  
Vol 16 (21) ◽  
pp. 821 ◽  
Author(s):  
Y. Kato ◽  
M. Dohsen ◽  
J. Kasahara ◽  
N. Watanabe
Keyword(s):  
High Speed ◽  
Logic Circuits

scholarly journals Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

2018 ◽  
Vol 8 (4) ◽  
pp. 37 ◽  
Author(s):  
Giovanna Turvani ◽  
Laura D’Alessandro ◽  
Marco Vacca
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Micromagnetic Simulations ◽  
Electrical Fields ◽  
Nanomagnet Logic ◽  
Nanomagnetic Logic ◽  
Elastic Effect ◽  
Physical Simulations ◽  
A Chain ◽  
Beyond Cmos

Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

High-Speed Logic, Circuits, Libraries and Layout

2005 ◽  
pp. 101-144
Author(s):  
Andrew Chang ◽  
William J. Dally ◽  
David Chinnery ◽  
Kurt Keutzer ◽  
Radu Zlatanovici
Keyword(s):  
High Speed ◽  
Logic Circuits

scholarly journals Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

2003 ◽  
Vol 13 (2) ◽  
pp. 523-526 ◽  
Author(s):  
N. Yoshikawa ◽  
K. Yoda ◽  
H. Hoshina ◽  
K. Kawasaki ◽  
K. Fujiwara ◽  
...  
Keyword(s):  
High Speed ◽  
Design Methodology ◽  
Large Scale ◽  
Logic Circuits ◽  
Speed Test

Normally-off type GaAs MESFET for low power, high speed logic circuits

1977 ◽  
Author(s):  
H. Ishikawa ◽  
H. Kusakawa ◽  
K. Suyama ◽  
M. Fukuta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Gaas Mesfet

Interconnection of High-Speed Logic Circuits

1970 ◽  
Vol C-19 (9) ◽  
pp. 831-837 ◽  
Author(s):  
T. Janisz ◽  
R.C. Martin
Keyword(s):  
High Speed ◽  
Logic Circuits
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