A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

2001 ◽  
Author(s):  
Hiroaki Yamaoka ◽  
Makoto Ikeda ◽  
Kunihiro Asada
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Charge Sharing ◽  
Sharing Scheme ◽  
Sense Amplifiers ◽  
A Charge

scholarly journals A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 385
Author(s):  
Qiao Wang ◽  
Donglin Zhang ◽  
Yulin Zhao ◽  
Chao Liu ◽  
Qiao Hu ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Reliability ◽  
Charge Sharing ◽  
Operation Speed ◽  
Sharing Function ◽  
Logic Operations ◽  
A Charge ◽  
Process Compatibility ◽  
Ferroelectric Capacitors

Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

Planar GaAs normally-off j.f.e.t. for high speed logic circuits

1980 ◽  
Vol 16 (21) ◽  
pp. 821 ◽  
Author(s):  
Y. Kato ◽  
M. Dohsen ◽  
J. Kasahara ◽  
N. Watanabe
Keyword(s):  
High Speed ◽  
Logic Circuits

scholarly journals Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

2018 ◽  
Vol 8 (4) ◽  
pp. 37 ◽  
Author(s):  
Giovanna Turvani ◽  
Laura D’Alessandro ◽  
Marco Vacca
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Micromagnetic Simulations ◽  
Electrical Fields ◽  
Nanomagnet Logic ◽  
Nanomagnetic Logic ◽  
Elastic Effect ◽  
Physical Simulations ◽  
A Chain ◽  
Beyond Cmos

Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

High-Speed Logic, Circuits, Libraries and Layout

2005 ◽  
pp. 101-144
Author(s):  
Andrew Chang ◽  
William J. Dally ◽  
David Chinnery ◽  
Kurt Keutzer ◽  
Radu Zlatanovici
Keyword(s):  
High Speed ◽  
Logic Circuits
Sign in / Sign up

Export Citation Format

Share Document