A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

2005 ◽  
Vol 40 (7) ◽  
pp. 1499-1505 ◽  
Author(s):  
C. Sandner ◽  
M. Clara ◽  
A. Santner ◽  
T. Hartig ◽  
F. Kuttner
Keyword(s):  
Low Power ◽  
Digital Cmos ◽  
Flash Adc

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

2017 ◽  
Vol 11 (6) ◽  
pp. 589-596 ◽  
Author(s):  
Anil Singh ◽  
Veena Rawat ◽  
Alpana Agarwal
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Pipelined Adc ◽  
Digital Cmos

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

Sign in / Sign up

Export Citation Format

Share Document