Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology

2004 ◽  
Author(s):  
Z.O. Gursoy ◽  
Y. Leblebici
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Data Recovery ◽  
Digital Cmos

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

scholarly journals A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

2020 ◽  
Author(s):  
Konstantinos Moustakas ◽  
P. Rymaszewski ◽  
T. Hemperek ◽  
H. Krüger ◽  
M. Vogt ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Front End

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

2000 ◽  
Vol 31 (11-12) ◽  
pp. 893-904 ◽  
Author(s):  
V. Liberali ◽  
R. Rossi ◽  
G. Torelli
Keyword(s):  
Cmos Technology ◽  
Deep Submicron ◽  
Digital Cmos ◽  
Mixed Signal
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