Controlling carrier trapping and relaxation with a dipole field in an organic field-effect device

RSC Advances ◽  
2016 ◽  
Vol 6 (81) ◽  
pp. 77735-77744 ◽  
Author(s):  
Yu-Fu Wang ◽  
Min-Ruei Tsai ◽  
Po-Yang Wang ◽  
Chin-Yang Lin ◽  
Horng-Long Cheng ◽  
...  
Keyword(s):  
Memory Effect ◽  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Charge Trapping ◽  
Dipole Field ◽  
Organic Transistors ◽  
Electrical Stability ◽  
Carrier Trapping

A novel polyimide electret using as the gate dielectric layer and charge trapping layer of n-type organic transistors was synthesized to improve the memory effect and electrical stability.

All-organic field effect transistors

2003 ◽  
Vol 769 ◽  
Author(s):  
R. Parashkov ◽  
E. Becker ◽  
G. Ginev ◽  
D. Schneider ◽  
D. Metzdorf ◽  
...  
Keyword(s):  
Active Layer ◽  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Operating Time ◽  
Aqueous Dispersion ◽  
Organic Transistors ◽  
Gate Structure ◽  
Top Gate Structure

AbstractIn this work we present fully patterned organic transistors based on selective electropolymerization of conducting polymers that enables simple fabrication of micron scale features. It involves fabrication of pentacene field effect transistors in which the conducting, insulating parts as well as the substrate are all made of polymers. We have fabricated drain and source electrodes by electropolymerization of 3,4- ethylenedioxythiophene and gate by spin coating of commercially available poly( 3,4- ethylenedioxythiophene) (PEDOT:PSS) aqueous dispersion, polyvinylalcohol for the gate dielectric layer, and pentacene for the organic active layer. We have built a top-gate structure with gate dielectric layer and gate placed on the top of the pentacene layer, and in a such way obtained protection of the active layer could permit enhancement of the operating time of devices. Carrier mobility as large as 0,01 cm2/V s was measured. Functional all- organic transistors have been realised using a simple and potentially inexpensive technology.

A flexible magnetoelectric field-effect transistor with magnetically responsive nanohybrid gate dielectric layer

Nano Research ◽  
2015 ◽  
Vol 8 (10) ◽  
pp. 3421-3429 ◽  
Author(s):  
Nguyen Minh Triet ◽  
Tran Quang Trung ◽  
Nguyen Thi Dieu Hien ◽  
Saqib Siddiqui ◽  
Do-Il Kim ◽  
...  
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Effect Transistor

High current density InN∕AlN heterojunction field-effect transistor with a SiNx gate dielectric layer

2007 ◽  
Vol 90 (14) ◽  
pp. 142111 ◽  
Author(s):  
Yu-Syuan Lin ◽  
Shun-Hau Koa ◽  
Chih-Yuan Chan ◽  
Shawn S. H. Hsu ◽  
Hong-Mao Lee ◽  
...  
Keyword(s):  
Current Density ◽  
Dielectric Layer ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
High Current Density ◽  
High Current ◽  
Effect Transistor

scholarly journals Fabrication of Flexible Organic Field Effect Transistor Constructed with a Polymer Gate Dielectric Layer

Shinku ◽  
2006 ◽  
Vol 49 (3) ◽  
pp. 168-170
Author(s):  
Yonglong JIN ◽  
Shizuyasu OCHIAI ◽  
Goro SAWA ◽  
Yoshiyuki UCHIDA ◽  
Kenzo KOJIMA ◽  
...  
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Organic Field Effect Transistor ◽  
Effect Transistor

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

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