scholarly journals Electronic logic gates from three-segment nanowires featuring two p–n heterojunctions

2013 ◽  
Vol 5 (8) ◽  
pp. e59-e59 ◽  
Author(s):  
Nan Chen ◽  
Songhua Chen ◽  
Canbin Ouyang ◽  
Yanwen Yu ◽  
Taifeng Liu ◽  
...  
Keyword(s):  
2014 ◽  
Vol 5 (1) ◽  
Author(s):  
Fanben Meng ◽  
Yves-Marie Hervault ◽  
Qi Shao ◽  
Benhui Hu ◽  
Lucie Norel ◽  
...  

2010 ◽  
Vol 132 (25) ◽  
pp. 8557-8559 ◽  
Author(s):  
Fan Xia ◽  
Xiaolei Zuo ◽  
Renqiang Yang ◽  
Ryan J. White ◽  
Yi Xiao ◽  
...  

2007 ◽  
Vol 15 (11) ◽  
pp. 6831 ◽  
Author(s):  
Yannick K. Lize ◽  
Louis Christen ◽  
Moshe Nazarathy ◽  
Scott Nuccio ◽  
Xiaoxia Wu ◽  
...  

2017 ◽  
Vol 22 (2) ◽  
pp. 27-47
Author(s):  
Zakaria Al-Sheikh ◽  
◽  
Abdullah Qahtan ◽  
Abdul Raqib Asaad ◽  
◽  
...  

2018 ◽  
Vol 23 (2) ◽  
pp. 1-30
Author(s):  
عبدالله علي قاسم الحميدي ◽  
عبدالرقيب عبده أسعد

In this paper, the second part of the software library for the Ternary combinational logic components will be built based on VHDL language starting by the TXOR (Ternary XOR gate) and ending by the TPA (Ternary Parallel Adder). This second part is an extension to the library given in the first part of the study which was about the basic Ternary Logic Gates [1]. Keywords: Ternary logic, Ternary combinational logic components, VHDL language.


2013 ◽  
Vol 19 (22) ◽  
pp. 6961-6965 ◽  
Author(s):  
Yun-Mei Zhang ◽  
Li Zhang ◽  
Ru-Ping Liang ◽  
Jian-Ding Qiu

2016 ◽  
Vol E99.C (2) ◽  
pp. 285-292 ◽  
Author(s):  
Tran THI THU HUONG ◽  
Hiroshi SHIMADA ◽  
Yoshinao MIZUGAKI

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