Surface Modification by Plasma Etching and Plasma Patterning

1997 ◽  
Vol 101 (46) ◽  
pp. 9548-9554 ◽  
Author(s):  
Liming Dai ◽  
Hans J. Griesser ◽  
Albert W. H. Mau
Keyword(s):  
Surface Modification ◽  
Plasma Etching

Plasma etching treatment for surface modification of boron-doped diamond electrodes

2007 ◽  
Vol 52 (11) ◽  
pp. 3841-3848 ◽  
Author(s):  
Takeshi Kondo ◽  
Hiroyuki Ito ◽  
Kazuhide Kusakabe ◽  
Kazuhiro Ohkawa ◽  
Yasuaki Einaga ◽  
...  
Keyword(s):  
Surface Modification ◽  
Plasma Etching ◽  
Diamond Electrodes ◽  
Boron Doped Diamond ◽  
Boron Doped

Surface modification and etch process optimization of fused silica during reaction CHF3–Ar plasma etching

Optik ◽  
2016 ◽  
Vol 127 (1) ◽  
pp. 206-211 ◽  
Author(s):  
Laixi Sun ◽  
Huang Jin ◽  
Xin Ye ◽  
Hongjie Liu ◽  
Fengrui Wang ◽  
...  
Keyword(s):  
Surface Modification ◽  
Process Optimization ◽  
Plasma Etching ◽  
Fused Silica ◽  
Ar Plasma

scholarly journals Surface Modification of Electroosmotic Silicon Microchannel Using Thermal Dry Oxidation

2018 ◽  
Author(s):  
Tuan Norjihan Tuan Yaakub ◽  
Jumril Yunas ◽  
Rhonira Latif ◽  
Azrul Azlan Hamzah ◽  
Mohd Farhanulhakim Razip Wee ◽  
...  
Keyword(s):  
Surface Modification ◽  
Oxide Layer ◽  
Plasma Etching ◽  
Sio2 Layer ◽  
Channel Width ◽  
Channel Cross Section ◽  
Microchannel Array ◽  
Thermal Chamber ◽  
Dry Oxidation

A simple fabrication method in the surface modification of electroosmotic silicon microchannel using thermal dry oxidation is presented. The surface modification is done by coating the silicon surface with a silicon dioxide (SiO2) layer using thermal oxidation process. The process is aimed not only to improve the surface quality of the channel to be suitable for electroosmotic fluid transport but also to reduce the channel width using a simple technique. Initially, the parallel microchannel array with dimensions of 0.5 mm length and width ranging from 1.8 µm to 2 µm are created using plasma etching on the 2x2 cm <100> silicon substrate. The oxidation of silicon channel in a thermal chamber is then conducted to create the SiO2 layer. The layer properties and the quality of the surface are analyzed using SEM and surface profiler, respectively. The results show that the maximum oxidation growth rate occurs in the first 4 hours of oxidation time and the rate decreases by time as the oxide layer becomes thicker. It is also found that the surface roughness is reduced with the increase of process temperature and oxide thickness. The scallop effect on the vertical wall due to plasma etching process also improved with the presence of the oxide layer. After the oxidation, the channel width is reduced by ~40%. The demonstrated method is suggested for the fabrication of a uniform channel cross section with high aspect ratio in sub-micro and nanometer scale that will be useful for the electroosmotic flow (EOF) manipulation of the biomedical fluid sample.

Surface modification by plasma etching impairs early vascularization and tissue incorporation of porous polyethylene (Medpor®) implants

2015 ◽  
Vol 104 (8) ◽  
pp. 1738-1748 ◽  
Author(s):  
Matthias W. Laschke ◽  
Victor A. Augustin ◽  
Fadime Sahin ◽  
Dieter Anschütz ◽  
Wolfgang Metzger ◽  
...  
Keyword(s):  
Surface Modification ◽  
Plasma Etching ◽  
Porous Polyethylene ◽  
Tissue Incorporation

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

1990 ◽  
Vol 48 (4) ◽  
pp. 566-567
Author(s):  
F. Banhart ◽  
F.O. Phillipp ◽  
R. Bergmann ◽  
E. Czech ◽  
M. Konuma ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Liquid Phase ◽  
Plasma Etching ◽  
Liquid Phase Epitaxy ◽  
Three Dimensional ◽  
Microscopical Study ◽  
Sample Temperature ◽  
Structural Defects ◽  
Si Substrates ◽  
Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

Sign in / Sign up

Export Citation Format

Share Document