Investigation of the Internal Heterostructure of Highly Luminescent Quantum Dot−Quantum Well Nanocrystals

2009 ◽  
Vol 131 (2) ◽  
pp. 470-477 ◽  
Author(s):  
Pralay K. Santra ◽  
Ranjani Viswanatha ◽  
Steve M. Daniels ◽  
Nigel L. Pickett ◽  
Jason M. Smith ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well

Gain-length scaling in quantum dot/quantum well infrared photodetectors

2009 ◽  
Vol 95 (9) ◽  
pp. 093502 ◽  
Author(s):  
T. Yamanaka ◽  
B. Movaghar ◽  
S. Tsao ◽  
S. Kuboya ◽  
A. Myzaferi ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Infrared Photodetectors ◽  
Quantum Well Infrared Photodetectors ◽  
Gain Length ◽  
Length Scaling

Quantum well and quantum dot infrared photodetectors: physics of operation and modeling

2003 ◽  
Author(s):  
Victor Ryzhii ◽  
Maxim Ryzhii ◽  
Irina Khmyrova ◽  
Robert Suris ◽  
Vladimir Mitin ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Infrared Photodetectors ◽  
Quantum Dot Infrared Photodetectors

scholarly journals Few electron double quantum dot in an isotopically purified 28Si quantum well

2012 ◽  
Vol 100 (14) ◽  
pp. 143110 ◽  
Author(s):  
A. Wild ◽  
J. Kierig ◽  
J. Sailer ◽  
J. W. Ager ◽  
E. E. Haller ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Double Quantum ◽  
Double Quantum Dot

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

InGaAs/GaAs quantum-dot–quantum-well heterostructure formed by submonolayer deposition

2003 ◽  
Vol 14 (12) ◽  
pp. 1259-1261 ◽  
Author(s):  
Zhangcheng Xu ◽  
Kristjan Leosson ◽  
Dan Birkedal ◽  
Vadim Lyssenko ◽  
Jørn M Hvam ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Gaas Quantum Dot
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