Scalable, High-Performance Printed InOx Transistors Enabled by Ultraviolet-Annealed Printed High-k AlOx Gate Dielectrics

2018 ◽  
Vol 10 (43) ◽  
pp. 37277-37286 ◽  
Author(s):  
William J. Scheideler ◽  
Matthew W. McPhail ◽  
Rajan Kumar ◽  
Jeremy Smith ◽  
Vivek Subramanian
Keyword(s):  
High Performance ◽  
Gate Dielectrics ◽  
High K

High Performance Aluminum-Doped ZnO Thin Film Transistors with High-K Gate Dielectrics Fabricated at Low Temperature

2013 ◽  
Vol 11 (8) ◽  
pp. 1509-1512 ◽  
Author(s):  
Dedong Han ◽  
Jian Cai ◽  
Wei Wang ◽  
Liangliang Wang ◽  
Yi Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
High Performance ◽  
Gate Dielectrics ◽  
Zno Thin Film ◽  
High K ◽  
Doped Zno

Surface-Modified High-k Oxide Gate Dielectrics for Low-Voltage High-Performance Pentacene Thin-Film Transistors

2007 ◽  
Vol 17 (6) ◽  
pp. 958-962 ◽  
Author(s):  
C. S. Kim ◽  
S. J. Jo ◽  
S. W. Lee ◽  
W. J. Kim ◽  
H. K. Baik ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
High Performance ◽  
Low Voltage ◽  
Gate Dielectrics ◽  
High K ◽  
Surface Modified

scholarly journals Fully solution-induced high performance indium oxide thin film transistors with ZrOx high-k gate dielectrics

RSC Advances ◽  
2018 ◽  
Vol 8 (30) ◽  
pp. 16788-16799 ◽  
Author(s):  
Li Zhu ◽  
Gang He ◽  
Jianguo Lv ◽  
Elvira Fortunato ◽  
Rodrigo Martins
Keyword(s):  
Thin Film ◽  
Flexible Electronics ◽  
Thin Film Transistors ◽  
High Performance ◽  
Gate Dielectrics ◽  
Low Cost ◽  
Oxide Thin Film ◽  
Viable Option ◽  
High K ◽  
Indium Oxide Thin Film

Solution based deposition has been recently considered as a viable option for low-cost flexible electronics.

High-performance high-k SmTiO3 gate dielectrics for amorphous InGaZnO thin-film transistor applications

2012 ◽  
Author(s):  
F. H. Chen ◽  
M. N. Hung ◽  
H. Y. Chen ◽  
J. H. Liu ◽  
J. L. Her ◽  
...  
Keyword(s):  
Thin Film ◽  
High Performance ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
High K ◽  
Amorphous Ingazno

Evaluation of Hafnium Contamination on Wafer Surfaces after the Wet Cleaning Process

2012 ◽  
Vol 195 ◽  
pp. 265-268
Author(s):  
Suguru Saito ◽  
Yoshiya Hagimoto ◽  
Hayato Iwamoto
Keyword(s):  
High Performance ◽  
Gate Dielectrics ◽  
Wafer Surface ◽  
Cleaning Process ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Gate Electrodes ◽  
High K ◽  
Device Properties ◽  
Wafer Surfaces

High-k gate dielectrics and metal gate electrodes have become essential for emerging device technologies because they enable the continuous scaling down of devices while maintaining a high performance [. However, since they are composed of novel metallic elements that have never before been used in conventional processes, special care must be taken when handling these materials in the production line. In particular, cross-contamination that occurs due to transporting contamination via processed wafers can cause serious problems such as deterioration of device properties and yield loss [. The process of cleaning the backside and bevel of a wafer is now increasingly important for avoiding these problems. To date, there has been no detailed evaluation of contamination removal on various films performed for elements such as hafnium, which is one of the key elements in high-k/metal gate technologies. In this study, we evaluated hafnium contamination on three types of wafer surface after the cleaning process and investigated the cause of different residual amounts of hafnium contamination on the different wafers.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Interfacial polarization-induced high-k polymer dielectric film for high-performance triboelectric devices

Nano Energy ◽  
2021 ◽  
Vol 82 ◽  
pp. 105697
Author(s):  
Minsoo P. Kim ◽  
Chang Won Ahn ◽  
Youngsu Lee ◽  
Kyoungho Kim ◽  
Jonghwa Park ◽  
...  
Keyword(s):  
High Performance ◽  
Dielectric Film ◽  
Interfacial Polarization ◽  
Polymer Dielectric ◽  
High K

High K gate dielectrics for the silicon industry

2002 ◽  
Author(s):  
L. Manchanda ◽  
B. Busch ◽  
M.L. Green ◽  
M. Morris ◽  
R.B. van Dover ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
High K
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