The electrical and structural properties of HfO2/SrTiO3 stacked gate dielectric with TiN metal gate electrode

2012 ◽  
Vol 521 ◽  
pp. 42-44 ◽  
Author(s):  
Changhwan Choi ◽  
Rino Choi
Keyword(s):  
Structural Properties ◽  
Gate Dielectric ◽  
Gate Electrode ◽  
Metal Gate ◽  
Tin Metal

scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

Compatibility of HfxTayN metal gate electrode with HfOxNy gate dielectric for advanced CMOS technology

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2516-2521
Author(s):  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang
Keyword(s):  
Gate Dielectric ◽  
Cmos Technology ◽  
Gate Electrode ◽  
Metal Gate

Dummy Oxide Removal in High-K Last Process Integration how to Avoid Silicon Corrosion Issue

2012 ◽  
Vol 195 ◽  
pp. 13-16 ◽  
Author(s):  
Farid Sebaai ◽  
Anabela Veloso ◽  
Hiroaki Takahashi ◽  
Antoine Pacco ◽  
Martine Claes ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Process Integration ◽  
Gate Electrode ◽  
Metal Gate ◽  
Poly Silicon ◽  
High K ◽  
Etch Stop ◽  
Etch Stop Layer ◽  
Oxide Removal ◽  
In The Beginning

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).

scholarly journals SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls

2012 ◽  
Vol 7 (2) ◽  
pp. 107-112
Author(s):  
Michele Rodrigues ◽  
Milene Galeti ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Crystallographic Orientation ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Electrode Thickness ◽  
Tin Metal ◽  
Output Conductance

This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-channel devices, when implemented on the rotated layout, offer a lower intrinsic voltage gain.The GIDL current was also analyzed on these devices, indicating to be larger in thinner metal gate and rotated configuration.

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