Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development

2009 ◽  
Vol 55 (7-9) ◽  
pp. 373-386 ◽  
Author(s):  
Mostafa E. Salehi ◽  
Sied Mehdi Fakhraie
Keyword(s):  
Quantitative Analysis ◽  
Packet Processing ◽  
Processing Engine ◽  
Engine Development ◽  
Network Processing

A Method for the Stateful Data-Plane Algorithm State Synchronization in the Network Processing Unit

2021 ◽  
Vol 33 (4) ◽  
pp. 69-76
Author(s):  
Yaroslav Konstantinovich Kuzmin ◽  
Dmitry Yuryevitch Volkanov ◽  
Julia Alexandrovna Skobtsova
Keyword(s):  
Processing Unit ◽  
Software Defined Networks ◽  
Packet Processing ◽  
Control Plane ◽  
Hardware Support ◽  
Control Information ◽  
Data Plane ◽  
Network Switches ◽  
Network Processing

This work presents a network processing unit based on specialized computational cores that is used for packet processing in network devices (e.g. in network switches). Nowadays stateful data-plane algorithms are developing in software-defined networks. The idea of stateful data-plane algorithms is to move a part of control information from control plane to data plane. But these algorithms require hardware support because they need resources for state handling. This work presents the network processing unit architecture modifications that allow to use stateful data-plane algorithms that require state synchronization between the NPU processing pipelines.

An In-DRAM Neural Network Processing Engine

2019 ◽  
Author(s):  
Chirag Sudarshan ◽  
Jan Lappas ◽  
Muhammad Mohsin Ghaffar ◽  
Vladimir Rybalkin ◽  
Christian Weis ◽  
...  
Keyword(s):  
Neural Network ◽  
Processing Engine ◽  
Network Processing

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

2007 ◽  
Vol 31 (3) ◽  
pp. 188-199 ◽  
Author(s):  
K. Vlachos ◽  
T. Orphanoudakis ◽  
Y. Papaeftathiou ◽  
N. Nikolaou ◽  
D. Pnevmatikatos ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Packet Processing ◽  
Network Processors ◽  
High Speed Network ◽  
And Performance ◽  
Processing Engine

ETA: experience with an intel xeon processor as a packet processing engine

IEEE Micro ◽  
2004 ◽  
Vol 24 (1) ◽  
pp. 24-31 ◽  
Author(s):  
G. Regnier ◽  
D. Minturn ◽  
G. McAlpine ◽  
V.A. Saletore ◽  
A. Foong
Keyword(s):  
Packet Processing ◽  
Processing Engine ◽  
Intel Xeon

scholarly journals DrawerPipe: A Reconfigurable Pipeline for Network Processing on FPGA-Based SmartNIC

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 59 ◽  
Author(s):  
Junnan Li ◽  
Zhigang Sun ◽  
Jinli Yan ◽  
Xiangrui Yang ◽  
Yue Jiang ◽  
...  
Keyword(s):  
High Performance ◽  
Packet Processing ◽  
The Public ◽  
Performance Requirements ◽  
Application Logic ◽  
Network Functions ◽  
Indexing Mechanism ◽  
Load Balancer ◽  
Rapid Deployment ◽  
Network Processing

In the public cloud, FPGA-based SmartNICs are widely deployed to accelerate network functions (NFs) for datacenter operators. We argue that with the trend of network as a service (NaaS) in the cloud is also meaningful to accelerate tenant NFs to meet performance requirements. However, in pursuit of high performance, existing work such as AccelNet is carefully designed to accelerate specific NFs for datacenter providers, which sacrifices the flexibility of rapidly deploying new NFs. For most tenants with limited hardware design ability, it is time-consuming to develop NFs from scratch due to the lack of a rapidly reconfigurable framework. In this paper, we present a reconfigurable network processing pipeline, i.e., DrawerPipe, which abstracts packet processing into multiple “drawers” connected by the same interface. NF developers can easily share existing modules with other NFs and simply load core application logic in the appropriate “drawer” to implement new NFs. Furthermore, we propose a programmable module indexing mechanism, namely PMI, which can connect “drawers” in any logical order, to perform distinct NFs for different tenants or flows. Finally, we implemented several highly reusable modules for low-level packet processing, and extended four example NFs (firewall, stateful firewall, load balancer, IDS) based on DrawerPipe. Our evaluation shows that DrawerPipe can easily offload customized packet processing to FPGA with high performance up to 100 Mpps and ultra-low latency (<10 µs). Moreover, DrawerPipe enables modular development of NFs, which is suitable for rapid deployment of NFs. Compared with individual NF development, DrawerPipe reduces the line of code (LoC) of the four NFs above by 68%.

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