Development of IPv6/IPv4 Translator Using High Performance Packet Processing Engine

2011 ◽  
Author(s):  
Ryo Sasaki ◽  
Makoto Otani ◽  
Kenzi Watanabe
Keyword(s):  
High Performance ◽  
Packet Processing ◽  
Processing Engine

scholarly journals High Performance Packet Processing with FlexNIC

2016 ◽  
Vol 51 (4) ◽  
pp. 67-81 ◽  
Author(s):  
Antoine Kaufmann ◽  
SImon Peter ◽  
Naveen Kr. Sharma ◽  
Thomas Anderson ◽  
Arvind Krishnamurthy
Keyword(s):  
High Performance ◽  
Packet Processing

scholarly journals High Performance Packet Processing with FlexNIC

2016 ◽  
Vol 44 (2) ◽  
pp. 67-81 ◽  
Author(s):  
Antoine Kaufmann ◽  
SImon Peter ◽  
Naveen Kr. Sharma ◽  
Thomas Anderson ◽  
Arvind Krishnamurthy
Keyword(s):  
High Performance ◽  
Packet Processing

scholarly journals An Adaptive Throughput-First Packet Scheduling Algorithm for DPDK-Based Packet Processing Systems

2021 ◽  
Vol 13 (3) ◽  
pp. 78
Author(s):  
Chuanhong Li ◽  
Lei Song ◽  
Xuewen Zeng
Keyword(s):  
Packet Loss ◽  
High Performance ◽  
Packet Scheduling ◽  
Scheduling Algorithm ◽  
Processing System ◽  
System Throughput ◽  
Packet Processing ◽  
Research Attention ◽  
Continuous Increase ◽  
Packet Scheduling Algorithm

The continuous increase in network traffic has sharply increased the demand for high-performance packet processing systems. For a high-performance packet processing system based on multi-core processors, the packet scheduling algorithm is critical because of the significant role it plays in load distribution, which is related to system throughput, attracting intensive research attention. However, it is not an easy task since the canonical flow-level packet scheduling algorithm is vulnerable to traffic locality, while the packet-level packet scheduling algorithm fails to maintain cache affinity. In this paper, we propose an adaptive throughput-first packet scheduling algorithm for DPDK-based packet processing systems. Combined with the feature of DPDK burst-oriented packet receiving and transmitting, we propose using Subflow as the scheduling unit and the adjustment unit making the proposed algorithm not only maintain the advantages of flow-level packet scheduling algorithms when the adjustment does not happen but also avoid packet loss as much as possible when the target core may be overloaded Experimental results show that the proposed method outperforms Round-Robin, HRW (High Random Weight), and CRC32 on system throughput and packet loss rate.

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

2021 ◽  
Author(s):  
Salvatore Di Girolamo ◽  
Andreas Kurth ◽  
Alexandru Calotoiu ◽  
Thomas Benz ◽  
Timo Schneider ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Packet Processing
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