scholarly journals Analysis of Interface Charge Using Capacitance-Voltage Method for Ultra Thin HfO2 Gate Dielectric Based MOS Devices

2015 ◽  
Vol 57 ◽  
pp. 757-760 ◽  
Author(s):  
N.P. Maity ◽  
R.R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Gate Dielectric ◽  
Mos Devices ◽  
Interface Charge ◽  
Capacitance Voltage

AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices

2009 ◽  
Vol 615-617 ◽  
pp. 541-544 ◽  
Author(s):  
Takuji Hosoi ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Yuu Watanabe ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Flat Band ◽  
Aluminum Oxynitride ◽  
Fixed Charges ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
High Dielectric ◽  
Mis Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H-SiC MIS devices. Since direct deposition of AlON on 4H-SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance-voltage hysteresis (30 mV), indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9), as compared to single N2O-SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high-temperature, especially in a high electric field condition (>5 MV/cm).

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High-$\kappa$ Gated MOS Devices

2007 ◽  
Vol 28 (5) ◽  
pp. 432-435 ◽  
Author(s):  
Chun-Yuan Lu ◽  
Kuei-Shu Chang-Liao ◽  
Chun-Chang Lu ◽  
Ping-Hung Tsai ◽  
Tien-Ko Wang
Keyword(s):  
Energy Distribution ◽  
Gate Dielectric ◽  
Trap Density ◽  
Mos Devices

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

Plasma-assisted chemical vapor deposited silicon oxynitride as an alternative material for gate dielectric in MOS devices

2006 ◽  
Vol 37 (1) ◽  
pp. 64-70 ◽  
Author(s):  
A. Szekeres ◽  
T. Nikolova ◽  
S. Simeonov ◽  
A. Gushterov ◽  
F. Hamelmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Chemical Vapor ◽  
Silicon Oxynitride ◽  
Mos Devices ◽  
Chemical Vapor Deposited ◽  
Alternative Material

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

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