scholarly journals Influence of Source/Drain Residual Implant Lattice Damage Traps on Silicon Carbide Metal Semiconductor Field-Effect Transistor Drain I-V Characteristics

2012 ◽  
Vol 25 ◽  
pp. 158-169
Author(s):  
J. Adjaye ◽  
M.S. Mazzola
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Lattice Damage ◽  
Effect Transistor

Improved Performance of Stair-Stepping Buffer-Gate 4H Silicon Carbide Metal Semiconductor Field Effect Transistor

2020 ◽  
Vol 209 (1) ◽  
pp. 11-18
Author(s):  
Xianjun Zhang ◽  
Na Li ◽  
Mingjia Wang ◽  
Qingliang Qin ◽  
Haohua Qin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Improved Performance

Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

2018 ◽  
Vol 924 ◽  
pp. 949-952 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Dorothy Lukco ◽  
Liang Yu Chen ◽  
Michael J. Krasowski ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Earth Atmosphere ◽  
Surface Atmosphere ◽  
Effect Transistor ◽  
Output Characteristics ◽  
Technology Demonstrator

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 837-842
Author(s):  
Xiao Chuan Deng ◽  
Hao Zhu ◽  
Xuan Li ◽  
Xiao Jie Xu ◽  
Kun Zhou ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Single Pulse ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Safe Operation ◽  
Effect Transistor ◽  
The Impact

In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energy are confirmed.

A silicon carbide nanowire field effect transistor for DNA detection

2016 ◽  
Vol 27 (23) ◽  
pp. 235501 ◽  
Author(s):  
L Fradetal ◽  
E Bano ◽  
G Attolini ◽  
F Rossi ◽  
V Stambouli
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Dna Detection ◽  
Effect Transistor

A 69-mΩ 600-V-Class Hybrid JFET

2013 ◽  
Vol 740-742 ◽  
pp. 925-928 ◽  
Author(s):  
Satoru Akiyama ◽  
Haruka Shimizu ◽  
Natsuki Yokoyama ◽  
Tomohiro Tamaki ◽  
Sadayuki Koido ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Breakdown Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Low Voltage ◽  
Oxide Semiconductor ◽  
Deep Trench ◽  
Trench Structure ◽  
Effect Transistor ◽  
State Resistance

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

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