Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

2007 ◽  
Vol 8 (4) ◽  
pp. 336-342 ◽  
Author(s):  
Kwonwoo Shin ◽  
Sang Yoon Yang ◽  
Chanwoo Yang ◽  
Hayoung Jeon ◽  
Chan Eon Park
2006 ◽  
Vol 100 (2) ◽  
pp. 024513 ◽  
Author(s):  
Tsuyoshi Sekitani ◽  
Takao Someya ◽  
Takayasu Sakurai

2019 ◽  
Vol 7 (14) ◽  
pp. 4004-4012 ◽  
Author(s):  
Fan Zhang ◽  
Huaye Zhang ◽  
Lijie Zhu ◽  
Liang Qin ◽  
Yue Wang ◽  
...  

High-performance bottom-gate 2D-layered (PEA)2SnI4 field-effect transistors have been fabricated using PVA/CL-PVP as gate dielectric layers.


2004 ◽  
Vol 84 (19) ◽  
pp. 3789-3791 ◽  
Author(s):  
Yusaku Kato ◽  
Shingo Iba ◽  
Ryohei Teramoto ◽  
Tsuyoshi Sekitani ◽  
Takao Someya ◽  
...  

2006 ◽  
Vol 99 (2) ◽  
pp. 024508 ◽  
Author(s):  
Z. M. Rittersma ◽  
J. C. Hooker ◽  
G. Vellianitis ◽  
J.-P. Locquet ◽  
C. Marchiori ◽  
...  

Small ◽  
2014 ◽  
pp. n/a-n/a ◽  
Author(s):  
Chong Guan Low ◽  
Qing Zhang ◽  
Yufeng Hao ◽  
Rodney S. Ruoff

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