High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

2019 ◽  
Vol 93 ◽  
pp. 89-97 ◽  
Author(s):  
Hongchen Li ◽  
Liyi Xiao ◽  
Jie Li ◽  
Chunhua Qi
Keyword(s):  
Cost Effective ◽  
Cmos Technology ◽  
Nanoscale Cmos

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

2015 ◽  
Vol E98.C (12) ◽  
pp. 1171-1178 ◽  
Author(s):  
Aibin YAN ◽  
Huaguo LIANG ◽  
Zhengfeng HUANG ◽  
Cuiyun JIANG ◽  
Maoxiang YI
Keyword(s):  
Cost Effective ◽  
Cmos Technology ◽  
Nanoscale Cmos

scholarly journals A Novel Chaotic Neural Network Using Memristive Synapse with Applications in Associative Memory

2012 ◽  
Vol 2012 ◽  
pp. 1-19 ◽  
Author(s):  
Xiaofang Hu ◽  
Shukai Duan ◽  
Lidan Wang
Keyword(s):  
Neural Network ◽  
Associative Memory ◽  
Large Scale ◽  
Cmos Technology ◽  
Chaotic Neural Network ◽  
Circuit Element ◽  
Nanoscale Cmos ◽  
Dynamical Behaviors ◽  
Implementation Scheme ◽  
Further Development

Chaotic Neural Network, also denoted by the acronym CNN, has rich dynamical behaviors that can be harnessed in promising engineering applications. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit. This paper addresses an implementation scheme of a novel CNN with memristive neural synapses that may provide a feasible solution for further development of CNN. Memristor, widely known as the fourth fundamental circuit element, was theoretically predicted by Chua in 1971 and has been developed in 2008 by the researchers in Hewlett-Packard Laboratory. Memristor based hybrid nanoscale CMOS technology is expected to revolutionize the digital and neuromorphic computation. The proposed memristive CNN has four significant features: (1) nanoscale memristors can simplify the synaptic circuit greatly and enable the synaptic weights update easily; (2) it can separate stored patterns from superimposed input; (3) it can deal with one-to-many associative memory; (4) it can deal with many-to-many associative memory. Simulation results are provided to illustrate the effectiveness of the proposed scheme.

The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000001-000005 ◽  
Author(s):  
R. Beica ◽  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
J. Azemar
Keyword(s):  
Semiconductor Industry ◽  
Cost Effective ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Current Trends ◽  
Advanced Packaging ◽  
Scaling Process ◽  
Market Trends ◽  
The Cost ◽  
Technology Nodes

The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package. This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.

Size Independent Sensitivity to Biomolecular Surface Density Using Nanoscale CMOS Technology Transistors

2020 ◽  
Vol 20 (16) ◽  
pp. 8956-8964
Author(s):  
Mihir Gupta ◽  
Sybren Santermans ◽  
Bert Du Bois ◽  
Rita Vos ◽  
Simone Severi ◽  
...  
Keyword(s):  
Surface Density ◽  
Cmos Technology ◽  
Nanoscale Cmos ◽  
Biomolecular Surface

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2577-2584
Author(s):  
James N. Pan
Keyword(s):  
Quantum Wells ◽  
High Frequency ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Cost Effective ◽  
Cmos Technology ◽  
Access Time ◽  
Cmos Process ◽  
Atomic Force

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

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