Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology

2012 ◽  
Vol 52 (1) ◽  
pp. 130-136 ◽  
Author(s):  
Bingxu Ning ◽  
Zhengxuan Zhang ◽  
Zhangli Liu ◽  
Zhiyuan Hu ◽  
Ming Chen ◽  
...  
Keyword(s):  
Flash Memory ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Radiation Induced

A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory

2018 ◽  
Vol 10 (3) ◽  
pp. 378-382
Author(s):  
Dandan Jiang ◽  
Lei Jin ◽  
Zongliang Huo
Keyword(s):  
Flash Memory ◽  
Drain Current ◽  
Parameter Extraction ◽  
Dose Effect ◽  
Total Ionizing Dose ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Radiation Behavior ◽  
Post Radiation ◽  
Net Positive Charge

To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.

High Performance Shallow Trench Isolation for High Density Flash Memory Cells

1996 ◽  
Author(s):  
S. Deleonibus ◽  
M. Heitzmann ◽  
Y. Gobil ◽  
F. Martin ◽  
O. Demolliens ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
High Density ◽  
Memory Cells ◽  
Shallow Trench Isolation ◽  
Trench Isolation

scholarly journals Superior PSZ-SOD Gap-Fill Process Integration Using Ultra-Low Dispensation Amount in STI for 28 nm NAND Flash Memory and Beyond

2015 ◽  
Vol 2015 ◽  
pp. 1-7
Author(s):  
Chun Chi Lai ◽  
Yi Wen Lu ◽  
Hung Ju Chien ◽  
Tzung Hua Ying
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Process Integration ◽  
Additional Treatment ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Liner Surface ◽  
28 Nm

The gap-fill performance and process of perhydropolysilazane-based inorganic spin-on dielectric (PSZ-SOD) film in shallow trench isolation (STI) with the ultra-low dispensation amount of PSZ-SOD solution have been investigated in this study. A PSZ-SOD film process includes liner deposition, PSZ-SOD coating, and furnace curing. For liner deposition, hydrophilic property is required to improve the contact angle and gap-fill capability of PSZ-SOD coating. Prior to PSZ-SOD coating, the additional treatment on liner surface is beneficial for the fluidity of PSZ-SOD solution. The superior film thickness uniformity and gap-fill performance of PSZ-SOD film are achieved due to the improved fluidity of PSZ-SOD solution. Following that up, the low dispensation rate of PSZ-SOD solution leads to more PSZ-SOD filling in the trenches. After PSZ-SOD coating, high thermal curing process efficiently promotes PSZ-SOD film conversion into silicon oxide. Adequate conversion from PSZ-SOD into silicon oxide further increases the etching resistance inside the trenches. Integrating the above sequence of optimized factors, void-free gap-fill and well-controlled STI recess uniformity are achieved even when the PSZ-SOD solution dispensation volume is reduced 3 to 6 times compared with conventional condition for the 28 nm node NAND flash and beyond.

Enhanced radiation-induced narrow channel effects in 0.13-${\boldsymbol{\mu }}{\rm{m}}$ PDSOI nMOSFETs with shallow trench isolation

2018 ◽  
Vol 27 (2) ◽  
pp. 028501 ◽  
Author(s):  
Meng-Ying Zhang ◽  
Zhi-Yuan Hu ◽  
Da-Wei Bi ◽  
Li-Hua Dai ◽  
Zheng-Xuan Zhang
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Channel Effects ◽  
Radiation Induced

Shallow Trench Isolation Edge Effect on Random Telegraph Signal Noise and Implications for Flash Memory

2009 ◽  
Vol 56 (9) ◽  
pp. 2107-2113 ◽  
Author(s):  
Ruey-Ven Wang ◽  
Yung-Huei Lee ◽  
Yin-Lung Ryan Lu ◽  
William McMahon ◽  
Sam Hu ◽  
...  
Keyword(s):  
Edge Effect ◽  
Flash Memory ◽  
Shallow Trench Isolation ◽  
Random Telegraph Signal ◽  
Signal Noise ◽  
Trench Isolation

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

2007 ◽  
Vol 124-126 ◽  
pp. 29-32
Author(s):  
Nam Hoon Kim ◽  
Hae Young Yoo ◽  
Eui Goo Chang
Keyword(s):  
Flash Memory ◽  
Chemical Mechanical Polishing ◽  
Gate Oxide ◽  
Mechanical Polishing ◽  
The Other ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Dry Oxidation ◽  
The Impact ◽  
Embedded Flash

The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.

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