Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1241-1246 ◽  
Author(s):  
R.P. Bastos ◽  
G. Sicard ◽  
F. Kastensmidt ◽  
M. Renaudin ◽  
R. Reis
Keyword(s):  
Asynchronous Circuits ◽  
Deep Submicron ◽  
Transient Faults ◽  
Long Duration

scholarly journals Tolerating Permanent Faults in the Input Port of the Network on Chip Router

2019 ◽  
Vol 9 (1) ◽  
pp. 11 ◽  
Author(s):  
Hala Mohammed ◽  
Wameedh Flayyih ◽  
Fakhrul Rokhani
Keyword(s):  
Network Performance ◽  
Deep Submicron ◽  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Transient Faults ◽  
Single Chip ◽  
Permanent Faults ◽  
Hardware Redundancy ◽  
On Chip

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

scholarly journals Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits

VLSI Design ◽  
2000 ◽  
Vol 11 (1) ◽  
pp. 23-34 ◽  
Author(s):  
Cecilia Metra ◽  
Michele Favalli ◽  
Bruno Riccò
Keyword(s):  
Deep Submicron ◽  
Transient Faults ◽  
Next Generation ◽  
Electrical Parameters ◽  
Parameter Variations ◽  
Increased Sensitivity ◽  
Functional Blocks ◽  
Internal Faults ◽  
Signal Coding

In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits with combinational functional blocks implemented also by next generation, very deep submicron technology. In particular, our functional blocks satisfy the Strongly Fault-Secure property with respect to a wide set of possible, internal faults including not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens, resistive bridgings, delays, crosstalks and transient faults, that are very likely to affect next generation ICs. Compared to alternative, existing solutions, that proposed here does not imply any critical constraint on the circuit electrical parameters. Therefore, it is suitable to be adopted to design very deep submicron self-checking circuits which, compared to todays' circuits, will present significantly increased sensitivity to parameter variations occurring during fabrication.

scholarly journals A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

2013 ◽  
Vol 29 (3) ◽  
pp. 331-340 ◽  
Author(s):  
Rodrigo Possamai Bastos ◽  
Giorgio Di Natale ◽  
Marie-Lise Flottes ◽  
Feng Lu ◽  
Bruno Rouzeyre
Keyword(s):  
Combinational Logic ◽  
Transient Faults ◽  
Long Duration ◽  
Recovery Scheme
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