Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

2008 ◽  
Vol 48 (4) ◽  
pp. 602-610 ◽  
Author(s):  
Xiaowu Zhang ◽  
Vaidyanathan Kripesh ◽  
T.C. Chai ◽  
Teck Chun Tan ◽  
D. Pinjala
Keyword(s):  
Solder Joint ◽  
Reliability Analysis ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Board Level ◽  
Wafer Level Package

Solder joint reliability of a polymer reinforced wafer level package

2002 ◽  
Vol 42 (12) ◽  
pp. 1837-1848 ◽  
Author(s):  
Deok-Hoon Kim ◽  
Peter Elenius ◽  
Michael Johnson ◽  
Scott Barrett
Keyword(s):  
Solder Joint ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

2020 ◽  
Vol 2020 (1) ◽  
pp. 000001-000004
Author(s):  
Dae-Suk Kim ◽  
Karthikeyan Dhandapani
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Crack Path ◽  
Path Selection ◽  
Circuit Board ◽  
Critical Element ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.

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