Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

2006 ◽  
Vol 46 (12) ◽  
pp. 2131-2138 ◽  
Author(s):  
Tong Yan Tee ◽  
Hun Shen Ng ◽  
Zhaowei Zhong
2008 ◽  
Vol 48 (4) ◽  
pp. 602-610 ◽  
Author(s):  
Xiaowu Zhang ◽  
Vaidyanathan Kripesh ◽  
T.C. Chai ◽  
Teck Chun Tan ◽  
D. Pinjala

2007 ◽  
Vol 4 (4) ◽  
pp. 186-194 ◽  
Author(s):  
C.I. Chen ◽  
S.C. Wu ◽  
D.S. Liu ◽  
C.Y. Ni ◽  
T. D. Yuan

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.


2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman

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